[PATCH v2 0/9] tcg: Use tcg_gen_[s]extract_{i32,i64,tl}

[PATCH v2 0/9] tcg: Use tcg_gen_[s]extract_{i32,i64,tl}

[Philippe Mathieu-Daudé]

Since v1:
- Dropped 2 RFC patches
- Added R-b tags
- Updated 'Use tcg_gen_ext() on MIPS'

Philippe Mathieu-Daudé (9):
  target/avr: Use tcg_gen_extract_tl
  target/cris: Use tcg_gen_extract_tl
  target/i386: Use tcg_gen_extract_tl
  target/mips: Use tcg_gen_extract_i32
  target/ppc: Use tcg_gen_extract_i32
  target/sparc: Use tcg_gen_extract_tl
  target/xtensa: Use tcg_gen_extract_i32
  target/mips: Use tcg_gen_ext16s_tl
  target/mips: Use tcg_gen_ext*u_tl

 target/avr/translate.c          | 18 ++----
 target/cris/translate.c         |  3 +-
 target/i386/tcg/translate.c     |  9 +--
 target/mips/tcg/mxu_translate.c | 98 ++++++++++++++++-----------------
 target/mips/tcg/translate.c     | 12 ++--
 target/ppc/translate.c          |  6 +-
 target/sparc/translate.c        |  6 +-
 target/xtensa/translate.c       |  6 +-
 8 files changed, 67 insertions(+), 91 deletions(-)

-- 
2.41.0

[PATCH v2 1/9] target/avr: Use tcg_gen_extract_tl

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
---
 target/avr/translate.c | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index cdffa04519..52fa7cebf6 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -223,8 +223,7 @@ static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
     tcg_gen_or_tl(t1, t1, t3);
 
     tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
-    tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
-    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+    tcg_gen_extract_tl(cpu_Hf, t1, 3, 1); /* Hf = t1(3) */
 }
 
 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
@@ -254,8 +253,7 @@ static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
     tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
 
     tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
-    tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
-    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+    tcg_gen_extract_tl(cpu_Hf, t2, 3, 1); /* Hf = t2(3) */
 }
 
 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
@@ -810,8 +808,7 @@ static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)
     /* update output registers */
     tcg_gen_shli_tl(R, R, 1);
     tcg_gen_andi_tl(R0, R, 0xff);
-    tcg_gen_shri_tl(R1, R, 8);
-    tcg_gen_andi_tl(R1, R1, 0xff);
+    tcg_gen_extract_tl(R1, R, 8, 8);
     return true;
 }
 
@@ -845,8 +842,7 @@ static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)
     /* update output registers */
     tcg_gen_shli_tl(R, R, 1);
     tcg_gen_andi_tl(R0, R, 0xff);
-    tcg_gen_shri_tl(R1, R, 8);
-    tcg_gen_andi_tl(R1, R1, 0xff);
+    tcg_gen_extract_tl(R1, R, 8, 8);
     return true;
 }
 
@@ -878,8 +874,7 @@ static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)
     /* update output registers */
     tcg_gen_shli_tl(R, R, 1);
     tcg_gen_andi_tl(R0, R, 0xff);
-    tcg_gen_shri_tl(R1, R, 8);
-    tcg_gen_andi_tl(R1, R1, 0xff);
+    tcg_gen_extract_tl(R1, R, 8, 8);
     return true;
 }
 
@@ -2020,8 +2015,7 @@ static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
     tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
     tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
     tcg_gen_andi_tl(L, addr, 0xff);
-    tcg_gen_shri_tl(addr, addr, 8);
-    tcg_gen_andi_tl(H, addr, 0xff);
+    tcg_gen_extract_tl(H, addr, 8, 8);
     return true;
 }
 
-- 
2.41.0

[PATCH v2 2/9] target/cris: Use tcg_gen_extract_tl

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
---
 target/cris/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/cris/translate.c b/target/cris/translate.c
index b3974ba0bb..65b07e1d80 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -871,8 +871,7 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
                 bits = 15;
             }
 
-            tcg_gen_shri_tl(cc, cc_result, bits);
-            tcg_gen_andi_tl(cc, cc, 1);
+            tcg_gen_extract_tl(cc, cc_result, bits, 1);
         } else {
             cris_evaluate_flags(dc);
             tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
-- 
2.41.0

[PATCH v2 3/9] target/i386: Use tcg_gen_extract_tl

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/tcg/translate.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 587d88692a..25289eeec9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1159,8 +1159,7 @@ static void gen_setcc1(DisasContext *s, int b, TCGv reg)
 
     if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 &&
         cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) {
-        tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask));
-        tcg_gen_andi_tl(reg, reg, 1);
+        tcg_gen_extract_tl(reg, cc.reg, ctztl(cc.mask), 1);
         return;
     }
     if (cc.mask != -1) {
@@ -1783,8 +1782,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
        currently dead.  */
     if (is_right) {
         tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask - 1);
-        tcg_gen_shri_tl(cpu_cc_dst, s->T0, mask);
-        tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
+        tcg_gen_extract_tl(cpu_cc_dst, s->T0, mask, 1);
     } else {
         tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask);
         tcg_gen_andi_tl(cpu_cc_dst, s->T0, 1);
@@ -1873,8 +1871,7 @@ static void gen_rot_rm_im(DisasContext *s, MemOp ot, int op1, int op2,
            currently dead.  */
         if (is_right) {
             tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask - 1);
-            tcg_gen_shri_tl(cpu_cc_dst, s->T0, mask);
-            tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
+            tcg_gen_extract_tl(cpu_cc_dst, s->T0, mask, 1);
         } else {
             tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask);
             tcg_gen_andi_tl(cpu_cc_dst, s->T0, 1);
-- 
2.41.0

[PATCH v2 4/9] target/mips: Use tcg_gen_extract_i32

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/tcg/translate.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 13e43fa3b6..2586d9c85a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1269,8 +1269,7 @@ static inline void gen_load_srsgpr(int from, int to)
         TCGv_ptr addr = tcg_temp_new_ptr();
 
         tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
-        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
-        tcg_gen_andi_i32(t2, t2, 0xf);
+        tcg_gen_extract_i32(t2, t2, CP0SRSCtl_PSS, 4);
         tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
         tcg_gen_ext_i32_ptr(addr, t2);
         tcg_gen_add_ptr(addr, tcg_env, addr);
@@ -1289,8 +1288,7 @@ static inline void gen_store_srsgpr(int from, int to)
 
         gen_load_gpr(t0, from);
         tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
-        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
-        tcg_gen_andi_i32(t2, t2, 0xf);
+        tcg_gen_extract_i32(t2, t2, CP0SRSCtl_PSS, 4);
         tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
         tcg_gen_ext_i32_ptr(addr, t2);
         tcg_gen_add_ptr(addr, tcg_env, addr);
@@ -8981,13 +8979,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
         tcg_gen_extu_i32_tl(bcond, t0);
         goto likely;
     case OPC_BC1T:
-        tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
-        tcg_gen_andi_i32(t0, t0, 1);
+        tcg_gen_extract_i32(t0, fpu_fcr31, get_fp_bit(cc), 1);
         tcg_gen_extu_i32_tl(bcond, t0);
         goto not_likely;
     case OPC_BC1TL:
-        tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
-        tcg_gen_andi_i32(t0, t0, 1);
+        tcg_gen_extract_i32(t0, fpu_fcr31, get_fp_bit(cc), 1);
         tcg_gen_extu_i32_tl(bcond, t0);
     likely:
         ctx->hflags |= MIPS_HFLAG_BL;
-- 
2.41.0

[PATCH v2 5/9] target/ppc: Use tcg_gen_extract_i32

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 329da4d518..c696fedbcc 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4802,16 +4802,14 @@ static void gen_mtcrf(DisasContext *ctx)
             TCGv_i32 temp = tcg_temp_new_i32();
             crn = ctz32(crm);
             tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
-            tcg_gen_shri_i32(temp, temp, crn * 4);
-            tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
+            tcg_gen_extract_i32(cpu_crf[7 - crn], temp, crn * 4, 4);
         }
     } else {
         TCGv_i32 temp = tcg_temp_new_i32();
         tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
         for (crn = 0 ; crn < 8 ; crn++) {
             if (crm & (1 << crn)) {
-                    tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
-                    tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
+                tcg_gen_extract_i32(cpu_crf[7 - crn], temp, crn * 4, 4);
             }
         }
     }
-- 
2.41.0

Re: [PATCH v2 5/9] target/ppc: Use tcg_gen_extract_i32

[Nicholas Piggin]

On Wed Oct 25, 2023 at 2:58 AM AEST, Philippe Mathieu-Daudé wrote:
> Inspired-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

> ---
>  target/ppc/translate.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 329da4d518..c696fedbcc 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4802,16 +4802,14 @@ static void gen_mtcrf(DisasContext *ctx)
>              TCGv_i32 temp = tcg_temp_new_i32();
>              crn = ctz32(crm);
>              tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
> -            tcg_gen_shri_i32(temp, temp, crn * 4);
> -            tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
> +            tcg_gen_extract_i32(cpu_crf[7 - crn], temp, crn * 4, 4);
>          }
>      } else {
>          TCGv_i32 temp = tcg_temp_new_i32();
>          tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
>          for (crn = 0 ; crn < 8 ; crn++) {
>              if (crm & (1 << crn)) {
> -                    tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
> -                    tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
> +                tcg_gen_extract_i32(cpu_crf[7 - crn], temp, crn * 4, 4);
>              }
>          }
>      }

[PATCH v2 6/9] target/sparc: Use tcg_gen_extract_tl

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f92ff80ac8..16d9151b90 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -740,14 +740,12 @@ static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
 static void gen_mov_reg_FCC0(TCGv reg, TCGv src,
                                     unsigned int fcc_offset)
 {
-    tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
-    tcg_gen_andi_tl(reg, reg, 0x1);
+    tcg_gen_extract_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset, 1);
 }
 
 static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset)
 {
-    tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
-    tcg_gen_andi_tl(reg, reg, 0x1);
+    tcg_gen_extract_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset, 1);
 }
 
 // !0: FCC0 | FCC1
-- 
2.41.0

[PATCH v2 7/9] target/xtensa: Use tcg_gen_extract_i32

[Philippe Mathieu-Daudé]

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/translate.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index de89940599..cbc564c020 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1595,11 +1595,7 @@ static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
 static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
                             const uint32_t par[])
 {
-    int maskimm = (1 << arg[3].imm) - 1;
-
-    TCGv_i32 tmp = tcg_temp_new_i32();
-    tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm);
-    tcg_gen_andi_i32(arg[0].out, tmp, maskimm);
+    tcg_gen_extract_i32(arg[0].out, arg[1].in, arg[2].imm, arg[3].imm);
 }
 
 static void translate_getex(DisasContext *dc, const OpcodeArg arg[],
-- 
2.41.0

[PATCH v2 8/9] target/mips: Use tcg_gen_ext16s_tl

[Philippe Mathieu-Daudé]

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/mxu_translate.c | 54 ++++++++++++++++-----------------
 1 file changed, 26 insertions(+), 28 deletions(-)

diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index c517258ac5..096a01e044 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1014,10 +1014,10 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,
      */
 
     gen_load_mxu_gpr(t1, XRb);
-    tcg_gen_sextract_tl(t0, t1, 0, 16);
+    tcg_gen_ext16s_tl(t0, t1);
     tcg_gen_sextract_tl(t1, t1, 16, 16);
     gen_load_mxu_gpr(t3, XRc);
-    tcg_gen_sextract_tl(t2, t3, 0, 16);
+    tcg_gen_ext16s_tl(t2, t3);
     tcg_gen_sextract_tl(t3, t3, 16, 16);
 
     switch (optn2) {
@@ -1113,11 +1113,11 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,
     aptn2 = extract32(ctx->opcode, 24, 2);
 
     gen_load_mxu_gpr(t1, XRb);
-    tcg_gen_sextract_tl(t0, t1, 0, 16);
+    tcg_gen_ext16s_tl(t0, t1);
     tcg_gen_sextract_tl(t1, t1, 16, 16);
 
     gen_load_mxu_gpr(t3, XRc);
-    tcg_gen_sextract_tl(t2, t3, 0, 16);
+    tcg_gen_ext16s_tl(t2, t3);
     tcg_gen_sextract_tl(t3, t3, 16, 16);
 
     switch (optn2) {
@@ -1234,11 +1234,11 @@ static void gen_mxu_d16madl(DisasContext *ctx)
     aptn2 = extract32(ctx->opcode, 24, 2);
 
     gen_load_mxu_gpr(t1, XRb);
-    tcg_gen_sextract_tl(t0, t1,  0, 16);
+    tcg_gen_ext16s_tl(t0, t1);
     tcg_gen_sextract_tl(t1, t1, 16, 16);
 
     gen_load_mxu_gpr(t3, XRc);
-    tcg_gen_sextract_tl(t2, t3,  0, 16);
+    tcg_gen_ext16s_tl(t2, t3);
     tcg_gen_sextract_tl(t3, t3, 16, 16);
 
     switch (optn2) {
@@ -1323,15 +1323,15 @@ static void gen_mxu_s16mad(DisasContext *ctx)
         tcg_gen_sextract_tl(t1, t1, 16, 16);
         break;
     case MXU_OPTN2_LW: /* XRB.L*XRC.L */
-        tcg_gen_sextract_tl(t0, t0,  0, 16);
-        tcg_gen_sextract_tl(t1, t1,  0, 16);
+        tcg_gen_ext16s_tl(t0, t0);
+        tcg_gen_ext16s_tl(t1, t1);
         break;
     case MXU_OPTN2_HW: /* XRB.H*XRC.L */
         tcg_gen_sextract_tl(t0, t0, 16, 16);
-        tcg_gen_sextract_tl(t1, t1,  0, 16);
+        tcg_gen_ext16s_tl(t1, t1);
         break;
     case MXU_OPTN2_XW: /* XRB.L*XRC.H */
-        tcg_gen_sextract_tl(t0, t0,  0, 16);
+        tcg_gen_ext16s_tl(t0, t0);
         tcg_gen_sextract_tl(t1, t1, 16, 16);
         break;
     }
@@ -1998,9 +1998,9 @@ static void gen_mxu_q16sxx(DisasContext *ctx, bool right, bool arithmetic)
 
     if (arithmetic) {
         tcg_gen_sextract_tl(t1, t0, 16, 16);
-        tcg_gen_sextract_tl(t0, t0,  0, 16);
+        tcg_gen_ext16s_tl(t0, t0);
         tcg_gen_sextract_tl(t3, t2, 16, 16);
-        tcg_gen_sextract_tl(t2, t2,  0, 16);
+        tcg_gen_ext16s_tl(t2, t2);
     } else {
         tcg_gen_extract_tl(t1, t0, 16, 16);
         tcg_gen_extract_tl(t0, t0,  0, 16);
@@ -2066,9 +2066,9 @@ static void gen_mxu_q16sxxv(DisasContext *ctx, bool right, bool arithmetic)
 
     if (arithmetic) {
         tcg_gen_sextract_tl(t1, t0, 16, 16);
-        tcg_gen_sextract_tl(t0, t0,  0, 16);
+        tcg_gen_ext16s_tl(t0, t0);
         tcg_gen_sextract_tl(t3, t2, 16, 16);
-        tcg_gen_sextract_tl(t2, t2,  0, 16);
+        tcg_gen_ext16s_tl(t2, t2);
     } else {
         tcg_gen_extract_tl(t1, t0, 16, 16);
         tcg_gen_extract_tl(t0, t0,  0, 16);
@@ -2492,8 +2492,8 @@ static void gen_mxu_D16SLT(DisasContext *ctx)
         tcg_gen_sextract_tl(t1, t4, 16, 16);
         tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
         tcg_gen_shli_tl(t2, t0, 16);
-        tcg_gen_sextract_tl(t0, t3,  0, 16);
-        tcg_gen_sextract_tl(t1, t4,  0, 16);
+        tcg_gen_ext16s_tl(t0, t3);
+        tcg_gen_ext16s_tl(t1, t4);
         tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
         tcg_gen_or_tl(mxu_gpr[XRa - 1], t2, t0);
     }
@@ -2547,8 +2547,8 @@ static void gen_mxu_d16avg(DisasContext *ctx, bool round45)
         }
         tcg_gen_shli_tl(t2, t0, 15);
         tcg_gen_andi_tl(t2, t2, 0xffff0000);
-        tcg_gen_sextract_tl(t0, t3,  0, 16);
-        tcg_gen_sextract_tl(t1, t4,  0, 16);
+        tcg_gen_ext16s_tl(t0, t3);
+        tcg_gen_ext16s_tl(t1, t4);
         tcg_gen_add_tl(t0, t0, t1);
         if (round45) {
             tcg_gen_addi_tl(t0, t0, 1);
@@ -2844,9 +2844,9 @@ static void gen_mxu_D16CPS(DisasContext *ctx)
         gen_set_label(l_done_hi);
         tcg_gen_shli_i32(t1, t1, 16);
 
-        tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1],  0, 16);
+        tcg_gen_ext16s_tl(t0, mxu_gpr[XRc - 1]);
         tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_not_less_lo);
-        tcg_gen_sextract_tl(t0, mxu_gpr[XRb - 1],  0, 16);
+        tcg_gen_ext16s_tl(t0, mxu_gpr[XRb - 1]);
         tcg_gen_subfi_tl(t0, 0, t0);
         tcg_gen_br(l_done_lo);
 
@@ -3388,7 +3388,7 @@ static void gen_mxu_d16asum(DisasContext *ctx)
     gen_load_mxu_gpr(t3, XRc);
 
     if (XRa != 0) {
-        tcg_gen_sextract_tl(t0, t2,  0, 16);
+        tcg_gen_ext16s_tl(t0, t2);
         tcg_gen_sextract_tl(t1, t2, 16, 16);
         tcg_gen_add_tl(t0, t0, t1);
         if (aptn2 & 2) {
@@ -3399,7 +3399,7 @@ static void gen_mxu_d16asum(DisasContext *ctx)
     }
 
     if (XRd != 0) {
-        tcg_gen_sextract_tl(t0, t3,  0, 16);
+        tcg_gen_ext16s_tl(t0, t3);
         tcg_gen_sextract_tl(t1, t3, 16, 16);
         tcg_gen_add_tl(t0, t0, t1);
         if (aptn2 & 1) {
@@ -3840,8 +3840,7 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)
             tcg_gen_movi_tl(t0, 255);
 
             gen_set_label(l_lo);
-            tcg_gen_shli_tl(t1, mxu_gpr[XRb - 1], 16);
-            tcg_gen_sari_tl(t1, t1, 16);
+            tcg_gen_ext16s_tl(t1, mxu_gpr[XRb - 1]);
             tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);
             tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);
             tcg_gen_br(l_done);
@@ -3876,8 +3875,7 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)
             tcg_gen_movi_tl(t0, 255);
 
             gen_set_label(l_lo);
-            tcg_gen_shli_tl(t1, mxu_gpr[XRc - 1], 16);
-            tcg_gen_sari_tl(t1, t1, 16);
+            tcg_gen_ext16s_tl(t1, mxu_gpr[XRc - 1]);
             tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);
             tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);
             tcg_gen_br(l_done);
@@ -3942,7 +3940,7 @@ static void gen_mxu_q16scop(DisasContext *ctx)
     tcg_gen_movi_tl(t3, 0x00010000);
 
     gen_set_label(l_b_lo);
-    tcg_gen_sextract_tl(t2, t0, 0, 16);
+    tcg_gen_ext16s_tl(t2, t0);
     tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_c_hi);
     tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_lo_lt);
     tcg_gen_ori_tl(t3, t3, 0x00000001);
@@ -3964,7 +3962,7 @@ static void gen_mxu_q16scop(DisasContext *ctx)
     tcg_gen_movi_tl(t4, 0x00010000);
 
     gen_set_label(l_c_lo);
-    tcg_gen_sextract_tl(t2, t1, 0, 16);
+    tcg_gen_ext16s_tl(t2, t1);
     tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_done);
     tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_lo_lt);
     tcg_gen_ori_tl(t4, t4, 0x00000001);
-- 
2.41.0

Re: [PATCH v2 8/9] target/mips: Use tcg_gen_ext16s_tl

[Richard Henderson]

On 10/24/23 09:59, Philippe Mathieu-Daudé wrote:
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/mxu_translate.c | 54 ++++++++++++++++-----------------
>   1 file changed, 26 insertions(+), 28 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH v2 9/9] target/mips: Use tcg_gen_ext*u_tl

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/mxu_translate.c | 44 ++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 096a01e044..451fbd7664 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -823,7 +823,7 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)
     switch (optn3) {
     /* XRa[7:0] => tmp8 */
     case MXU_OPTN3_PTN0:
-        tcg_gen_extract_tl(t1, t1, 0, 8);
+        tcg_gen_ext8u_tl(t1, t1);
         break;
     /* XRa[15:8] => tmp8 */
     case MXU_OPTN3_PTN1:
@@ -931,7 +931,7 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)
     switch (optn2) {
     /* XRa[15:0] => tmp16 */
     case MXU_OPTN2_PTN0:
-        tcg_gen_extract_tl(t1, t1, 0, 16);
+        tcg_gen_ext16u_tl(t1, t1);
         break;
     /* XRa[31:16] => tmp16 */
     case MXU_OPTN2_PTN1:
@@ -1259,8 +1259,8 @@ static void gen_mxu_d16madl(DisasContext *ctx)
         tcg_gen_mul_tl(t2, t1, t2);
         break;
     }
-    tcg_gen_extract_tl(t2, t2, 0, 16);
-    tcg_gen_extract_tl(t3, t3, 0, 16);
+    tcg_gen_ext16u_tl(t2, t2);
+    tcg_gen_ext16u_tl(t3, t3);
 
     gen_load_mxu_gpr(t1, XRa);
     tcg_gen_extract_tl(t0, t1,  0, 16);
@@ -1961,7 +1961,7 @@ static void gen_mxu_d32sarl(DisasContext *ctx, bool sarw)
         gen_load_mxu_gpr(t1, XRc);
         tcg_gen_sar_tl(t0, t0, t2);
         tcg_gen_sar_tl(t1, t1, t2);
-        tcg_gen_extract_tl(t2, t1, 0, 16);
+        tcg_gen_ext16u_tl(t2, t1);
         tcg_gen_deposit_tl(t2, t2, t0, 16, 16);
         gen_store_mxu_gpr(t2, XRa);
     }
@@ -2667,9 +2667,9 @@ static void gen_mxu_q8movzn(DisasContext *ctx, TCGCond cond)
     tcg_gen_deposit_tl(t2, t2, t3, 8, 8);
 
     gen_set_label(l_quarterrest);
-    tcg_gen_extract_tl(t3, t1, 0, 8);
+    tcg_gen_ext8u_tl(t3, t1);
     tcg_gen_brcondi_tl(cond, t3, 0, l_done);
-    tcg_gen_extract_tl(t3, t0, 0, 8);
+    tcg_gen_ext8u_tl(t3, t0);
     tcg_gen_deposit_tl(t2, t2, t3, 0, 8);
 
     gen_set_label(l_done);
@@ -2714,9 +2714,9 @@ static void gen_mxu_d16movzn(DisasContext *ctx, TCGCond cond)
     tcg_gen_deposit_tl(t2, t2, t3, 16, 16);
 
     gen_set_label(l_halfdone);
-    tcg_gen_extract_tl(t3, t1, 0, 16);
+    tcg_gen_ext16u_tl(t3, t1);
     tcg_gen_brcondi_tl(cond, t3, 0, l_done);
-    tcg_gen_extract_tl(t3, t0, 0, 16);
+    tcg_gen_ext16u_tl(t3, t0);
     tcg_gen_deposit_tl(t2, t2, t3, 0, 16);
 
     gen_set_label(l_done);
@@ -2851,7 +2851,7 @@ static void gen_mxu_D16CPS(DisasContext *ctx)
         tcg_gen_br(l_done_lo);
 
         gen_set_label(l_not_less_lo);
-        tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1],  0, 16);
+        tcg_gen_ext16u_tl(t0, mxu_gpr[XRb - 1]);
 
         gen_set_label(l_done_lo);
         tcg_gen_deposit_tl(mxu_gpr[XRa - 1], t1, t0, 0, 16);
@@ -3033,7 +3033,7 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)
                 tcg_gen_add_tl(t2, t2, t3);
             }
             tcg_gen_shli_tl(t2, t2, 16);
-            tcg_gen_extract_tl(t0, t0, 0, 16);
+            tcg_gen_ext16u_tl(t0, t0);
             tcg_gen_or_tl(t4, t2, t0);
         }
         if (XRd != 0) {
@@ -3056,7 +3056,7 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)
                 tcg_gen_add_tl(t2, t2, t3);
             }
             tcg_gen_shli_tl(t2, t2, 16);
-            tcg_gen_extract_tl(t0, t0, 0, 16);
+            tcg_gen_ext16u_tl(t0, t0);
             tcg_gen_or_tl(t5, t2, t0);
         }
 
@@ -3156,11 +3156,11 @@ static void gen_mxu_q16add(DisasContext *ctx)
     TCGv t5 = tcg_temp_new();
 
     gen_load_mxu_gpr(t1, XRb);
-    tcg_gen_extract_tl(t0, t1,  0, 16);
+    tcg_gen_ext16u_tl(t0, t1);
     tcg_gen_extract_tl(t1, t1, 16, 16);
 
     gen_load_mxu_gpr(t3, XRc);
-    tcg_gen_extract_tl(t2, t3,  0, 16);
+    tcg_gen_ext16u_tl(t2, t3);
     tcg_gen_extract_tl(t3, t3, 16, 16);
 
     switch (optn2) {
@@ -3210,9 +3210,9 @@ static void gen_mxu_q16add(DisasContext *ctx)
     }
 
     tcg_gen_shli_tl(t0, t0, 16);
-    tcg_gen_extract_tl(t1, t1, 0, 16);
+    tcg_gen_ext16u_tl(t1, t1);
     tcg_gen_shli_tl(t4, t4, 16);
-    tcg_gen_extract_tl(t5, t5, 0, 16);
+    tcg_gen_ext16u_tl(t5, t5);
 
     tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5);
     tcg_gen_or_tl(mxu_gpr[XRd - 1], t0, t1);
@@ -3242,11 +3242,11 @@ static void gen_mxu_q16acc(DisasContext *ctx)
     TCGv s0 = tcg_temp_new();
 
     gen_load_mxu_gpr(t1, XRb);
-    tcg_gen_extract_tl(t0, t1,  0, 16);
+    tcg_gen_ext16u_tl(t0, t1);
     tcg_gen_extract_tl(t1, t1, 16, 16);
 
     gen_load_mxu_gpr(t3, XRc);
-    tcg_gen_extract_tl(t2, t3,  0, 16);
+    tcg_gen_ext16u_tl(t2, t3);
     tcg_gen_extract_tl(t3, t3, 16, 16);
 
     switch (aptn2) {
@@ -3278,7 +3278,7 @@ static void gen_mxu_q16acc(DisasContext *ctx)
 
     if (XRa != 0) {
         tcg_gen_add_tl(t0, mxu_gpr[XRa - 1], s0);
-        tcg_gen_extract_tl(t0, t0, 0, 16);
+        tcg_gen_ext16u_tl(t0, t0);
         tcg_gen_extract_tl(t1, mxu_gpr[XRa - 1], 16, 16);
         tcg_gen_add_tl(t1, t1, s1);
         tcg_gen_shli_tl(t1, t1, 16);
@@ -3287,7 +3287,7 @@ static void gen_mxu_q16acc(DisasContext *ctx)
 
     if (XRd != 0) {
         tcg_gen_add_tl(t0, mxu_gpr[XRd - 1], s2);
-        tcg_gen_extract_tl(t0, t0, 0, 16);
+        tcg_gen_ext16u_tl(t0, t0);
         tcg_gen_extract_tl(t1, mxu_gpr[XRd - 1], 16, 16);
         tcg_gen_add_tl(t1, t1, s3);
         tcg_gen_shli_tl(t1, t1, 16);
@@ -3335,7 +3335,7 @@ static void gen_mxu_q16accm(DisasContext *ctx)
             tcg_gen_add_tl(a0, a0, t0);
             tcg_gen_add_tl(a1, a1, t1);
         }
-        tcg_gen_extract_tl(a0, a0, 0, 16);
+        tcg_gen_ext16u_tl(a0, a0);
         tcg_gen_shli_tl(a1, a1, 16);
         tcg_gen_or_tl(mxu_gpr[XRa - 1], a1, a0);
     }
@@ -3358,7 +3358,7 @@ static void gen_mxu_q16accm(DisasContext *ctx)
             tcg_gen_add_tl(a0, a0, t0);
             tcg_gen_add_tl(a1, a1, t1);
         }
-        tcg_gen_extract_tl(a0, a0, 0, 16);
+        tcg_gen_ext16u_tl(a0, a0);
         tcg_gen_shli_tl(a1, a1, 16);
         tcg_gen_or_tl(mxu_gpr[XRd - 1], a1, a0);
     }
-- 
2.41.0

Re: [PATCH v2 9/9] target/mips: Use tcg_gen_ext*u_tl

[Richard Henderson]

On 10/24/23 09:59, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/mxu_translate.c | 44 ++++++++++++++++-----------------
>   1 file changed, 22 insertions(+), 22 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~