From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>
Subject: [PATCH v2 3/9] target/i386: Use tcg_gen_extract_tl
Date: Tue, 24 Oct 2023 18:58:56 +0200 [thread overview]
Message-ID: <20231024165903.40861-4-philmd@linaro.org> (raw)
In-Reply-To: <20231024165903.40861-1-philmd@linaro.org>
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 587d88692a..25289eeec9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1159,8 +1159,7 @@ static void gen_setcc1(DisasContext *s, int b, TCGv reg)
if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 &&
cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) {
- tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask));
- tcg_gen_andi_tl(reg, reg, 1);
+ tcg_gen_extract_tl(reg, cc.reg, ctztl(cc.mask), 1);
return;
}
if (cc.mask != -1) {
@@ -1783,8 +1782,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
currently dead. */
if (is_right) {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask - 1);
- tcg_gen_shri_tl(cpu_cc_dst, s->T0, mask);
- tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
+ tcg_gen_extract_tl(cpu_cc_dst, s->T0, mask, 1);
} else {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask);
tcg_gen_andi_tl(cpu_cc_dst, s->T0, 1);
@@ -1873,8 +1871,7 @@ static void gen_rot_rm_im(DisasContext *s, MemOp ot, int op1, int op2,
currently dead. */
if (is_right) {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask - 1);
- tcg_gen_shri_tl(cpu_cc_dst, s->T0, mask);
- tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
+ tcg_gen_extract_tl(cpu_cc_dst, s->T0, mask, 1);
} else {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask);
tcg_gen_andi_tl(cpu_cc_dst, s->T0, 1);
--
2.41.0
next prev parent reply other threads:[~2023-10-24 17:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 16:58 [PATCH v2 0/9] tcg: Use tcg_gen_[s]extract_{i32,i64,tl} Philippe Mathieu-Daudé
2023-10-24 16:58 ` [PATCH v2 1/9] target/avr: Use tcg_gen_extract_tl Philippe Mathieu-Daudé
2023-10-24 16:58 ` [PATCH v2 2/9] target/cris: " Philippe Mathieu-Daudé
2023-10-24 16:58 ` Philippe Mathieu-Daudé [this message]
2023-10-24 16:58 ` [PATCH v2 4/9] target/mips: Use tcg_gen_extract_i32 Philippe Mathieu-Daudé
2023-10-24 16:58 ` [PATCH v2 5/9] target/ppc: " Philippe Mathieu-Daudé
2023-10-25 7:10 ` Nicholas Piggin
2023-10-24 16:58 ` [PATCH v2 6/9] target/sparc: Use tcg_gen_extract_tl Philippe Mathieu-Daudé
2023-10-24 16:59 ` [PATCH v2 7/9] target/xtensa: Use tcg_gen_extract_i32 Philippe Mathieu-Daudé
2023-10-24 16:59 ` [PATCH v2 8/9] target/mips: Use tcg_gen_ext16s_tl Philippe Mathieu-Daudé
2023-10-25 20:22 ` Richard Henderson
2023-10-24 16:59 ` [PATCH v2 9/9] target/mips: Use tcg_gen_ext*u_tl Philippe Mathieu-Daudé
2023-10-25 20:22 ` Richard Henderson
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