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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id gu18-20020a170906f29200b00977cad140a8sm10161364ejb.218.2023.10.25.09.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 09:05:46 -0700 (PDT) Date: Wed, 25 Oct 2023 18:05:45 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v4 1/9] target/riscv: add rva22u64 profile definition Message-ID: <20231025-3d85561bf6f08059fc7eb359@orel> References: <20231025135001.531224-1-dbarboza@ventanamicro.com> <20231025135001.531224-2-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231025135001.531224-2-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Oct 25, 2023 at 10:49:53AM -0300, Daniel Henrique Barboza wrote: > The rva22U64 profile, described in: > > https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles > > Contains a set of CPU extensions aimed for 64-bit userspace > applications. Enabling this set to be enabled via a single user flag > makes it convenient to enable a predictable set of features for the CPU, > giving users more predicability when running/testing their workloads. > > QEMU implements all possible extensions of this profile. The exception > is Zicbop (Cache-Block Prefetch Operations) that is not available since > QEMU RISC-V does not implement a cache model. For this same reason all > the so called 'synthetic extensions' described in the profile that are > cache related are ignored (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, > Zicclsm). > > An abstraction called RISCVCPUProfile is created to store the profile. > 'ext_offsets' contains mandatory extensions that QEMU supports. Same > thing with the 'misa_ext' mask. Optional extensions must be enabled > manually in the command line if desired. > > The design here is to use the common target/riscv/cpu.c file to store > the profile declaration and export it to the accelerator files. Each > accelerator is then responsible to expose it (or not) to users and how > to enable the extensions. > > Next patches will implement the profile for TCG and KVM. > > Signed-off-by: Daniel Henrique Barboza > Acked-by: Alistair Francis > --- > target/riscv/cpu.c | 20 ++++++++++++++++++++ > target/riscv/cpu.h | 12 ++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f40da4c661..c9e263cbac 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1429,6 +1429,26 @@ Property riscv_cpu_options[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +/* Optional extensions left out: RVV, zfh, zkn, zks */ > +static RISCVCPUProfile RVA22U64 = { > + .name = "rva22u64", > + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC, > + .ext_offsets = { > + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), > + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), > + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), > + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), > + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), > + CPU_CFG_OFFSET(ext_zicboz), There are several more mandatory RVA22U64 extensions in the ratified spec[1]. I think many of them can be "implemented" by QEMU by simply adding their names to the ISA string. But, in any case, I think we should at least put a comment here explaining why they're not in ext_offsets[] [1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf Thanks, drew