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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits
Date: Wed, 25 Oct 2023 18:24:50 +0200	[thread overview]
Message-ID: <20231025-be256dcdda482f9226679e8b@orel> (raw)
In-Reply-To: <20231025135001.531224-9-dbarboza@ventanamicro.com>

On Wed, Oct 25, 2023 at 10:50:00AM -0300, Daniel Henrique Barboza wrote:
> RVG behaves like a profile: a single flag enables a set of bits. Right
> now we're considering user choice when handling RVG and zicsr/zifencei
> and ignoring user choice on MISA bits.
> 
> We'll add user warnings for profiles when the user disables its
> mandatory extensions in the next patch. We'll do the same thing with RVG
> now to keep consistency between RVG and profile handling.
> 
> First and foremost, create a new RVG only helper to avoid clogging
> riscv_cpu_validate_set_extensions(). We do not want to annoy users with
> RVG warnings like we did in the past (see 9b9741c38f), thus we'll only
> warn if RVG was user set and the user disabled a RVG extension in the
> command line.
> 
> For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then
> becomes:
> 
> - if enabled, do nothing;
> - if disabled and not user set, enable it;
> - if disabled and user set, throw a warning that it's a RVG mandatory
>   extension.
> 
> This same logic will be used for profiles in the next patch.
> 
> Note that this is a behavior change, where we would error out if the
> user disabled either zicsr or zifencei. As long as users are explicitly
> disabling things in the command line we'll let them have a go at it, at
> least in this step. We'll error out later in the validation if needed.
> 
> Other notable changes from the previous RVG code:
> 
> - use riscv_cpu_write_misa_bit() instead of manually updating both
>   env->misa_ext and env->misa_ext_mask;
> 
> - set zicsr and zifencei directly. We're already checking if they
>   were user set and priv version will never fail for these
>   extensions, making cpu_cfg_ext_auto_update() redundant.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/tcg/tcg-cpu.c | 73 +++++++++++++++++++++++++-------------
>  1 file changed, 48 insertions(+), 25 deletions(-)
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


  reply	other threads:[~2023-10-25 16:25 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-25 13:49 [PATCH v4 0/9] RVA22U64 profile support Daniel Henrique Barboza
2023-10-25 13:49 ` [PATCH v4 1/9] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-25 16:05   ` Andrew Jones
2023-10-25 23:48   ` Richard Henderson
2023-10-25 23:49     ` Richard Henderson
2023-10-25 13:49 ` [PATCH v4 2/9] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-25 16:09   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 3/9] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-25 16:10   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 4/9] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-25 16:14   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 5/9] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-25 16:14   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-25 16:16   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-25 16:18   ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-25 16:24   ` Andrew Jones [this message]
2023-10-25 13:50 ` [PATCH v4 9/9] target/riscv/tcg: warn if profile exts are disabled Daniel Henrique Barboza
2023-10-25 16:28   ` Andrew Jones

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