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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id j14-20020a1709064b4e00b0099bd1a78ef5sm10204543ejv.74.2023.10.25.09.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 09:24:51 -0700 (PDT) Date: Wed, 25 Oct 2023 18:24:50 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits Message-ID: <20231025-be256dcdda482f9226679e8b@orel> References: <20231025135001.531224-1-dbarboza@ventanamicro.com> <20231025135001.531224-9-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231025135001.531224-9-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Oct 25, 2023 at 10:50:00AM -0300, Daniel Henrique Barboza wrote: > RVG behaves like a profile: a single flag enables a set of bits. Right > now we're considering user choice when handling RVG and zicsr/zifencei > and ignoring user choice on MISA bits. > > We'll add user warnings for profiles when the user disables its > mandatory extensions in the next patch. We'll do the same thing with RVG > now to keep consistency between RVG and profile handling. > > First and foremost, create a new RVG only helper to avoid clogging > riscv_cpu_validate_set_extensions(). We do not want to annoy users with > RVG warnings like we did in the past (see 9b9741c38f), thus we'll only > warn if RVG was user set and the user disabled a RVG extension in the > command line. > > For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then > becomes: > > - if enabled, do nothing; > - if disabled and not user set, enable it; > - if disabled and user set, throw a warning that it's a RVG mandatory > extension. > > This same logic will be used for profiles in the next patch. > > Note that this is a behavior change, where we would error out if the > user disabled either zicsr or zifencei. As long as users are explicitly > disabling things in the command line we'll let them have a go at it, at > least in this step. We'll error out later in the validation if needed. > > Other notable changes from the previous RVG code: > > - use riscv_cpu_write_misa_bit() instead of manually updating both > env->misa_ext and env->misa_ext_mask; > > - set zicsr and zifencei directly. We're already checking if they > were user set and priv version will never fail for these > extensions, making cpu_cfg_ext_auto_update() redundant. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/tcg/tcg-cpu.c | 73 +++++++++++++++++++++++++------------- > 1 file changed, 48 insertions(+), 25 deletions(-) > Reviewed-by: Andrew Jones