From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v4 4/9] target/riscv/tcg: add MISA user options hash
Date: Wed, 25 Oct 2023 18:14:07 +0200 [thread overview]
Message-ID: <20231025-c1044818992ebc741dc8186b@orel> (raw)
In-Reply-To: <20231025135001.531224-5-dbarboza@ventanamicro.com>
On Wed, Oct 25, 2023 at 10:49:56AM -0300, Daniel Henrique Barboza wrote:
> We already track user choice for multi-letter extensions because we
> needed to honor user choice when enabling/disabling extensions during
> realize(). We refrained from adding the same mechanism for MISA
> extensions since we didn't need it.
>
> Profile support requires tne need to check for user choice for MISA
> extensions, so let's add the corresponding hash now. It works like the
> existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits
> options in the cpu_set_misa_ext_cfg() callback.
>
> Note that we can't re-use the same hash from multi-letter extensions
> because that hash uses cpu->cfg offsets as keys, while for MISA
> extensions we're using MISA bits as keys.
>
> After adding the user hash in cpu_set_misa_ext_cfg(), setting default
> values with object_property_set_bool() in add_misa_properties() will end
> up marking the user choice hash with them. Set the default value
> manually to avoid it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-10-25 16:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 13:49 [PATCH v4 0/9] RVA22U64 profile support Daniel Henrique Barboza
2023-10-25 13:49 ` [PATCH v4 1/9] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-25 16:05 ` Andrew Jones
2023-10-25 23:48 ` Richard Henderson
2023-10-25 23:49 ` Richard Henderson
2023-10-25 13:49 ` [PATCH v4 2/9] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-25 16:09 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 3/9] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-25 16:10 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 4/9] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-25 16:14 ` Andrew Jones [this message]
2023-10-25 13:49 ` [PATCH v4 5/9] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-25 16:14 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-25 16:16 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-25 16:18 ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-25 16:24 ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 9/9] target/riscv/tcg: warn if profile exts are disabled Daniel Henrique Barboza
2023-10-25 16:28 ` Andrew Jones
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