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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits
Date: Wed, 25 Oct 2023 18:16:05 +0200	[thread overview]
Message-ID: <20231025-fea5001cf2b2a92b81442b25@orel> (raw)
In-Reply-To: <20231025135001.531224-7-dbarboza@ventanamicro.com>

On Wed, Oct 25, 2023 at 10:49:58AM -0300, Daniel Henrique Barboza wrote:
> The profile support is handling multi-letter extensions only. Let's add
> support for MISA bits as well.
> 
> We'll go through every known MISA bit. If the profile doesn't declare the bit
> as mandatory, ignore it. Otherwise, set or clear the bit in env->misa_ext and
> env->misa_ext_mask depending on whether the profile was set to 'true' or
> 'false'.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>  target/riscv/tcg/tcg-cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index b2489a5317..57026cfcca 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -804,6 +804,19 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
>      profile->user_set = true;
>      profile->enabled = value;
>  
> +    for (i = 0; misa_bits[i] != 0; i++) {
> +        uint32_t bit = misa_bits[i];
> +
> +        if  (!(profile->misa_ext & bit)) {
> +            continue;
> +        }
> +
> +        g_hash_table_insert(misa_ext_user_opts,
> +                            GUINT_TO_POINTER(bit),
> +                            (gpointer)value);
> +        riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
> +    }
> +
>      for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
>          ext_offset = profile->ext_offsets[i];
>  
> -- 
> 2.41.0
> 
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


  reply	other threads:[~2023-10-25 16:16 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-25 13:49 [PATCH v4 0/9] RVA22U64 profile support Daniel Henrique Barboza
2023-10-25 13:49 ` [PATCH v4 1/9] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-25 16:05   ` Andrew Jones
2023-10-25 23:48   ` Richard Henderson
2023-10-25 23:49     ` Richard Henderson
2023-10-25 13:49 ` [PATCH v4 2/9] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-25 16:09   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 3/9] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-25 16:10   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 4/9] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-25 16:14   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 5/9] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-25 16:14   ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-25 16:16   ` Andrew Jones [this message]
2023-10-25 13:49 ` [PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-25 16:18   ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-25 16:24   ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 9/9] target/riscv/tcg: warn if profile exts are disabled Daniel Henrique Barboza
2023-10-25 16:28   ` Andrew Jones

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