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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id co2-20020a0564020c0200b0053ed70ebd7csm9777568edb.31.2023.10.25.09.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 09:16:06 -0700 (PDT) Date: Wed, 25 Oct 2023 18:16:05 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits Message-ID: <20231025-fea5001cf2b2a92b81442b25@orel> References: <20231025135001.531224-1-dbarboza@ventanamicro.com> <20231025135001.531224-7-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231025135001.531224-7-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Oct 25, 2023 at 10:49:58AM -0300, Daniel Henrique Barboza wrote: > The profile support is handling multi-letter extensions only. Let's add > support for MISA bits as well. > > We'll go through every known MISA bit. If the profile doesn't declare the bit > as mandatory, ignore it. Otherwise, set or clear the bit in env->misa_ext and > env->misa_ext_mask depending on whether the profile was set to 'true' or > 'false'. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: LIU Zhiwei > --- > target/riscv/tcg/tcg-cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index b2489a5317..57026cfcca 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -804,6 +804,19 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, > profile->user_set = true; > profile->enabled = value; > > + for (i = 0; misa_bits[i] != 0; i++) { > + uint32_t bit = misa_bits[i]; > + > + if (!(profile->misa_ext & bit)) { > + continue; > + } > + > + g_hash_table_insert(misa_ext_user_opts, > + GUINT_TO_POINTER(bit), > + (gpointer)value); > + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); > + } > + > for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { > ext_offset = profile->ext_offsets[i]; > > -- > 2.41.0 > > Reviewed-by: Andrew Jones