From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension
Date: Wed, 25 Oct 2023 23:13:27 +0800 [thread overview]
Message-ID: <20231025151341.725477-4-max.chou@sifive.com> (raw)
In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com>
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index d8d17dedeed..935335e5721 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -88,6 +88,7 @@ struct RISCVCPUConfig {
bool ext_zve64d;
bool ext_zvbb;
bool ext_zvbc;
+ bool ext_zvkb;
bool ext_zvkg;
bool ext_zvkned;
bool ext_zvknha;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b9eaecb699c..1b08f27eee4 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -508,9 +508,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
* In principle Zve*x would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
- cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
- !cpu->cfg.ext_zve32f) {
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
+ cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
error_setg(errp,
"Vector crypto extensions require V or Zve* extensions");
return;
--
2.34.1
next prev parent reply other threads:[~2023-10-25 15:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
2023-10-30 4:47 ` Alistair Francis
2023-10-25 15:13 ` [PATCH 02/14] target/riscv: Expose Zvkt extension property Max Chou
2023-10-25 15:13 ` Max Chou [this message]
2023-10-25 15:13 ` [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb Max Chou
2023-10-25 15:13 ` [PATCH 05/14] target/riscv: Expose Zvkb extension property Max Chou
2023-10-25 15:13 ` [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
2023-10-25 15:13 ` [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
2023-10-25 15:13 ` [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou
2023-10-25 15:13 ` [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
2023-10-25 15:13 ` [PATCH 14/14] disas/riscv: Replace TABs with space Max Chou
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