From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Nazar Kazakov <nazar.kazakov@codethink.co.uk>,
Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Subject: [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb
Date: Wed, 25 Oct 2023 23:13:28 +0800 [thread overview]
Message-ID: <20231025151341.725477-5-max.chou@sifive.com> (raw)
In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com>
The Zvkb extension is a proper subset of the Zvbb extension and includes
following instructions:
* vandn.[vv,vx]
* vbrev8.v
* vrev8.v
* vrol.[vv,vx]
* vror.[vv,vx,vi]
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++++++++++++++---------
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index e691519ed78..3801c16829d 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -112,24 +112,27 @@ GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
return false; \
}
-static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a)
+static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a)
{
- return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true;
+ return opivv_check(s, a) &&
+ (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true);
}
-static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a)
+static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a)
{
- return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true;
+ return opivx_check(s, a) &&
+ (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true);
}
/* vrol.v[vx] */
-GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check)
-GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check)
+GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvkb_vv_check)
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvkb_vx_check)
/* vror.v[vxi] */
-GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check)
-GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check)
-GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check)
+GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvkb_vv_check)
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvkb_vx_check)
+GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri,
+ zvkb_vx_check)
#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
@@ -147,8 +150,8 @@ GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check
}
/* vandn.v[vx] */
-GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check)
-GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
+GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvkb_vv_check)
+GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
#define GEN_OPIV_TRANS(NAME, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
@@ -188,8 +191,16 @@ static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
vext_check_ss(s, a->rd, a->rs2, a->vm);
}
-GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check)
-GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check)
+static bool zvkb_opiv_check(DisasContext *s, arg_rmr *a)
+{
+ return (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true) &&
+ require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
+}
+
+GEN_OPIV_TRANS(vbrev8_v, zvkb_opiv_check)
+GEN_OPIV_TRANS(vrev8_v, zvkb_opiv_check)
GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check)
GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check)
GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check)
--
2.34.1
next prev parent reply other threads:[~2023-10-25 15:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
2023-10-30 4:47 ` Alistair Francis
2023-10-25 15:13 ` [PATCH 02/14] target/riscv: Expose Zvkt extension property Max Chou
2023-10-25 15:13 ` [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension Max Chou
2023-10-25 15:13 ` Max Chou [this message]
2023-10-25 15:13 ` [PATCH 05/14] target/riscv: Expose Zvkb extension property Max Chou
2023-10-25 15:13 ` [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
2023-10-25 15:13 ` [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
2023-10-25 15:13 ` [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou
2023-10-25 15:13 ` [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
2023-10-25 15:13 ` [PATCH 14/14] disas/riscv: Replace TABs with space Max Chou
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