From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions
Date: Wed, 25 Oct 2023 23:13:32 +0800 [thread overview]
Message-ID: <20231025151341.725477-9-max.chou@sifive.com> (raw)
In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com>
Vector crypto spec defines the ShangMi algorithm suite related
extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto
extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fd07aa96a27..7b0ca657a6a 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -99,6 +99,9 @@ struct RISCVCPUConfig {
bool ext_zvkn;
bool ext_zvknc;
bool ext_zvkng;
+ bool ext_zvks;
+ bool ext_zvksc;
+ bool ext_zvksg;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index e460701a13c..f9023ca75c7 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -519,6 +519,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
}
+ if (cpu->cfg.ext_zvksc) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
+ }
+
+ if (cpu->cfg.ext_zvksg) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
+ }
+
+ if (cpu->cfg.ext_zvks) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
+ }
+
if (cpu->cfg.ext_zvkt) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
--
2.34.1
next prev parent reply other threads:[~2023-10-25 15:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
2023-10-30 4:47 ` Alistair Francis
2023-10-25 15:13 ` [PATCH 02/14] target/riscv: Expose Zvkt extension property Max Chou
2023-10-25 15:13 ` [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension Max Chou
2023-10-25 15:13 ` [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb Max Chou
2023-10-25 15:13 ` [PATCH 05/14] target/riscv: Expose Zvkb extension property Max Chou
2023-10-25 15:13 ` [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` Max Chou [this message]
2023-10-25 15:13 ` [PATCH 09/14] target/riscv: Expose Zvks[c|g] " Max Chou
2023-10-25 15:13 ` [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
2023-10-25 15:13 ` [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
2023-10-25 15:13 ` [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou
2023-10-25 15:13 ` [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
2023-10-25 15:13 ` [PATCH 14/14] disas/riscv: Replace TABs with space Max Chou
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