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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id i6-20020a17090671c600b009920a690cd9sm11159820ejk.59.2023.10.26.01.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 01:31:52 -0700 (PDT) Date: Thu, 26 Oct 2023 10:31:51 +0200 From: Andrew Jones To: Sunil V L Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu Subject: Re: [PATCH v4 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT Message-ID: <20231026-5530c164173cd1859e9df666@orel> References: <20231025200713.580814-1-sunilvl@ventanamicro.com> <20231025200713.580814-10-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231025200713.580814-10-sunilvl@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Oct 26, 2023 at 01:37:09AM +0530, Sunil V L wrote: > MMU type information is available via MMU node in RHCT. Add this node in > RHCT. > > Signed-off-by: Sunil V L > Reviewed-by: Daniel Henrique Barboza > --- > hw/riscv/virt-acpi-build.c | 37 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 36 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index ebe7062b9b..dc7c0213f5 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -159,6 +159,8 @@ static void build_rhct(GArray *table_data, > size_t len, aligned_len; > uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; > RISCVCPU *cpu = &s->soc[0].harts[0]; > + uint32_t mmu_offset = 0; > + uint8_t satp_mode_max; > char *isa; > > AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, > @@ -178,6 +180,10 @@ static void build_rhct(GArray *table_data, > num_rhct_nodes++; > } > > + if (cpu->cfg.satp_mode.supported != 0) { > + num_rhct_nodes++; > + } > + > /* Number of RHCT nodes*/ > build_append_int_noprefix(table_data, num_rhct_nodes, 4); > > @@ -233,6 +239,26 @@ static void build_rhct(GArray *table_data, > } > } > > + /* MMU node structure */ > + if (cpu->cfg.satp_mode.supported != 0) { > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + mmu_offset = table_data->len - table.table_offset; > + build_append_int_noprefix(table_data, 2, 2); /* Type */ > + build_append_int_noprefix(table_data, 8, 2); /* Length */ > + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ > + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ > + /* MMU Type */ > + if (satp_mode_max == VM_1_10_SV57) { > + build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ > + } else if (satp_mode_max == VM_1_10_SV48) { > + build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ > + } else if (satp_mode_max == VM_1_10_SV39) { > + build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ > + } else { > + assert(1); > + } > + } > + > /* Hart Info Node */ > for (int i = 0; i < arch_ids->len; i++) { > len = 16; > @@ -245,17 +271,26 @@ static void build_rhct(GArray *table_data, > num_offsets++; > } > > + if (mmu_offset) { > + len += 4; > + num_offsets++; > + } > + > build_append_int_noprefix(table_data, len, 2); > build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ > /* Number of offsets */ > build_append_int_noprefix(table_data, num_offsets, 2); > build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ > - > /* Offsets */ > build_append_int_noprefix(table_data, isa_offset, 4); > + if (mmu_offset) { > + build_append_int_noprefix(table_data, mmu_offset, 4); > + } > + In the previous version of this patch the MMU node was getting generated above the CMO node, so its offset was less than those of the CMO node, and why I recommended moving it up here. But, in this version, the MMU node is now getting generated after the CMO node, so moving this up means the offsets are still not in ascending order. > if (cmo_offset) { > build_append_int_noprefix(table_data, cmo_offset, 4); > } > + > } > > acpi_table_end(linker, &table); > -- > 2.39.2 > > Anyway, Reviewed-by: Andrew Jones Thanks, drew