From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: [PULL 37/94] target/sparc: Move SUBC to decodetree
Date: Wed, 25 Oct 2023 17:14:45 -0700 [thread overview]
Message-ID: <20231026001542.1141412-67-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 139 ++++++++++++++++++++++++--------------
2 files changed, 90 insertions(+), 50 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index d6a7256e71..a188452d2e 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -165,6 +165,7 @@ ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc
ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
+SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index e7c3c68402..b8fbd18a4c 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -538,51 +538,11 @@ static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
- TCGv src2, int update_cc)
+static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv src2,
+ TCGv_i32 carry_32, bool update_cc)
{
- TCGv_i32 carry_32;
TCGv carry;
- switch (dc->cc_op) {
- case CC_OP_DIV:
- case CC_OP_LOGIC:
- /* Carry is known to be zero. Fall back to plain SUB. */
- if (update_cc) {
- gen_op_sub_cc(dst, src1, src2);
- } else {
- tcg_gen_sub_tl(dst, src1, src2);
- }
- return;
-
- case CC_OP_ADD:
- case CC_OP_TADD:
- case CC_OP_TADDTV:
- carry_32 = gen_add32_carry32();
- break;
-
- case CC_OP_SUB:
- case CC_OP_TSUB:
- case CC_OP_TSUBTV:
- if (TARGET_LONG_BITS == 32) {
- /* We can re-use the host's hardware carry generation by using
- a SUB2 opcode. We discard the low part of the output.
- Ideally we'd combine this operation with the add that
- generated the carry in the first place. */
- carry = tcg_temp_new();
- tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
- goto sub_done;
- }
- carry_32 = gen_sub32_carry32();
- break;
-
- default:
- /* We need external help to produce the carry. */
- carry_32 = tcg_temp_new_i32();
- gen_helper_compute_C_icc(carry_32, tcg_env);
- break;
- }
-
#if TARGET_LONG_BITS == 64
carry = tcg_temp_new();
tcg_gen_extu_i32_i64(carry, carry_32);
@@ -593,16 +553,75 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
tcg_gen_sub_tl(dst, src1, src2);
tcg_gen_sub_tl(dst, dst, carry);
- sub_done:
if (update_cc) {
+ tcg_debug_assert(dst == cpu_cc_dst);
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
- tcg_gen_mov_tl(cpu_cc_dst, dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
- dc->cc_op = CC_OP_SUBX;
}
}
+static void gen_op_subc_add(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), false);
+}
+
+static void gen_op_subccc_add(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), true);
+}
+
+static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool update_cc)
+{
+ TCGv discard;
+
+ if (TARGET_LONG_BITS == 64) {
+ gen_op_subc_int(dst, src1, src2, gen_sub32_carry32(), update_cc);
+ return;
+ }
+
+ /*
+ * We can re-use the host's hardware carry generation by using
+ * a SUB2 opcode. We discard the low part of the output.
+ */
+ discard = tcg_temp_new();
+ tcg_gen_sub2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
+
+ if (update_cc) {
+ tcg_debug_assert(dst == cpu_cc_dst);
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ }
+}
+
+static void gen_op_subc_sub(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_op_subc_int_sub(dst, src1, src2, false);
+}
+
+static void gen_op_subccc_sub(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_op_subc_int_sub(dst, src1, src2, true);
+}
+
+static void gen_op_subc_int_generic(TCGv dst, TCGv src1, TCGv src2,
+ bool update_cc)
+{
+ TCGv_i32 carry_32 = tcg_temp_new_i32();
+
+ gen_helper_compute_C_icc(carry_32, tcg_env);
+ gen_op_subc_int(dst, src1, src2, carry_32, update_cc);
+}
+
+static void gen_op_subc_generic(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_op_subc_int_generic(dst, src1, src2, false);
+}
+
+static void gen_op_subccc_generic(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_op_subc_int_generic(dst, src1, src2, true);
+}
+
static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp, zero, t0;
@@ -4144,6 +4163,30 @@ static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a)
}
}
+static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a)
+{
+ switch (dc->cc_op) {
+ case CC_OP_DIV:
+ case CC_OP_LOGIC:
+ /* Carry is known to be zero. Fall back to plain SUB. */
+ return do_arith(dc, a, CC_OP_SUB,
+ tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc);
+ case CC_OP_ADD:
+ case CC_OP_TADD:
+ case CC_OP_TADDTV:
+ return do_arith(dc, a, CC_OP_SUBX,
+ gen_op_subc_add, NULL, gen_op_subccc_add);
+ case CC_OP_SUB:
+ case CC_OP_TSUB:
+ case CC_OP_TSUBTV:
+ return do_arith(dc, a, CC_OP_SUBX,
+ gen_op_subc_sub, NULL, gen_op_subccc_sub);
+ default:
+ return do_arith(dc, a, CC_OP_SUBX,
+ gen_op_subc_generic, NULL, gen_op_subccc_generic);
+ }
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4568,10 +4611,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
- case 0xc: /* subx, V9 subc */
- gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
- (xop & 0x10));
- break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
--
2.34.1
next prev parent reply other threads:[~2023-10-26 0:33 UTC|newest]
Thread overview: 135+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-26 0:13 [PULL 00/94] target/sparc: Convert to decodetree Richard Henderson
2023-10-26 0:13 ` [PULL 01/94] target/sparc: Clear may_lookup for npc == DYNAMIC_PC Richard Henderson
2023-10-26 0:13 ` [PATCH 01/29] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:13 ` [PULL 02/94] target/sparc: Implement check_align inline Richard Henderson
2023-10-26 0:13 ` [PATCH 02/29] tcg/optimize: Split out arg_is_const_val Richard Henderson
2023-10-26 0:13 ` [PULL 03/94] target/sparc: Avoid helper_raise_exception in helper_st_asi Richard Henderson
2023-10-26 0:13 ` [PATCH 03/29] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2023-10-26 0:13 ` [PULL 04/94] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-26 0:13 ` [PATCH 04/29] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2023-10-26 0:13 ` [PULL 05/94] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-26 0:13 ` [PATCH 05/29] tcg/optimize: Split out arg_new_constant Richard Henderson
2023-10-26 0:13 ` [PULL 06/94] target/sparc: Define features via cpu-feature.h.inc Richard Henderson
2023-10-26 0:13 ` [PATCH 06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-27 2:05 ` Paolo Bonzini
2023-10-26 0:13 ` [PULL 07/94] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties Richard Henderson
2023-10-26 0:13 ` [PATCH 07/29] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:13 ` [PULL 08/94] target/sparc: Remove sparcv7 cpu features Richard Henderson
2023-10-26 0:13 ` [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2023-10-27 4:44 ` Paolo Bonzini
2023-10-26 0:13 ` [PULL 09/94] target/sparc: Partition cpu features Richard Henderson
2023-10-26 0:13 ` [PATCH 09/29] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:13 ` [PULL 10/94] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-26 0:13 ` [PATCH 10/29] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2023-10-26 0:14 ` [PULL 11/94] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-26 0:14 ` [PATCH 11/29] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2023-10-26 0:14 ` [PULL 12/94] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi Richard Henderson
2023-10-26 0:14 ` [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 13/29] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 11:29 ` Paolo Bonzini
2023-10-26 16:07 ` Richard Henderson
2023-10-27 2:15 ` Paolo Bonzini
2023-10-26 0:14 ` [PULL 14/94] target/sparc: Move BPr to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 14/29] tcg/loongarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 16/94] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-26 0:14 ` [PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 17/94] target/sparc: Merge gen_fcond with only caller Richard Henderson
2023-10-26 0:14 ` [PATCH 17/29] tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson
2023-10-26 0:14 ` [PULL 18/94] target/sparc: Merge gen_branch_[an] with only caller Richard Henderson
2023-10-26 0:14 ` [PATCH 18/29] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2023-10-26 0:14 ` [PULL 19/94] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-26 0:14 ` [PATCH 19/29] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2023-10-26 0:14 ` [PULL 20/94] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 20/29] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 21/94] target/sparc: Move Tcc to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 21/29] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2023-10-26 0:14 ` [PULL 22/94] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree Richard Henderson
2023-11-03 19:07 ` Peter Maydell
2023-11-03 22:54 ` Richard Henderson
2023-10-26 0:14 ` [PATCH 22/29] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2023-10-26 0:14 ` [PULL 23/94] target/sparc: Move RDPSR, RDHPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 23/29] tcg/ppc: Create tcg_out_and_rc Richard Henderson
2023-10-26 0:14 ` [PULL 24/94] target/sparc: Move RDWIM, RDPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 24/29] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 25/94] target/sparc: Move RDTBR, FLUSHW to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 25/29] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 26/94] target/sparc: Move WRASR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 26/29] tcg/tci: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PATCH 27/29] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2023-10-26 0:14 ` [PULL 27/94] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 28/29] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Richard Henderson
2023-10-26 0:14 ` [PULL 28/94] target/sparc: Move WRWIM, WRPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 29/29] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2023-10-26 0:14 ` [PULL 29/94] target/sparc: Move WRTBR, WRHPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PULL 30/94] target/sparc: Remove cpu_wim Richard Henderson
2023-10-26 0:14 ` [PULL 31/94] target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr Richard Henderson
2023-10-26 0:14 ` [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver Richard Henderson
2023-10-26 0:14 ` [PULL 33/94] target/sparc: Move basic arithmetic to decodetree Richard Henderson
2023-10-26 0:14 ` [PULL 34/94] target/sparc: Move ADDC " Richard Henderson
2023-10-26 0:14 ` [PULL 35/94] target/sparc: Move MULX " Richard Henderson
2023-10-26 0:14 ` [PULL 36/94] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-26 0:14 ` Richard Henderson [this message]
2023-10-26 0:14 ` [PULL 38/94] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-26 0:14 ` [PULL 39/94] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-26 0:14 ` [PULL 40/94] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-26 0:14 ` [PULL 41/94] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-26 0:14 ` [PULL 42/94] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-26 0:14 ` [PULL 43/94] target/sparc: Move POPC " Richard Henderson
2023-10-26 0:14 ` [PULL 44/94] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-26 0:14 ` [PULL 45/94] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-26 0:14 ` [PULL 46/94] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-26 0:14 ` [PULL 47/94] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-26 0:14 ` [PULL 48/94] target/sparc: Split out resolve_asi Richard Henderson
2023-10-26 0:14 ` [PULL 49/94] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-26 0:14 ` [PULL 50/94] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-26 0:14 ` [PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-26 0:15 ` [PULL 52/94] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 53/94] target/sparc: Move asi " Richard Henderson
2023-10-26 0:15 ` [PULL 54/94] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-26 0:15 ` [PULL 55/94] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-26 0:15 ` [PULL 56/94] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-26 0:15 ` [PULL 57/94] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-26 0:15 ` [PULL 58/94] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-26 0:15 ` [PULL 59/94] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 60/94] target/sparc: Move asi " Richard Henderson
2023-10-26 0:15 ` [PULL 61/94] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-26 0:15 ` [PULL 62/94] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-26 0:15 ` [PULL 63/94] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 64/94] target/sparc: Move ARRAY* " Richard Henderson
2023-10-26 0:15 ` [PULL 65/94] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-26 0:15 ` [PULL 66/94] target/sparc: Move BMASK " Richard Henderson
2023-10-26 0:15 ` [PULL 67/94] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-26 0:15 ` [PULL 68/94] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-26 0:15 ` [PULL 69/94] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-26 0:15 ` [PULL 70/94] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 71/94] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-26 0:15 ` [PULL 72/94] target/sparc: Move PDIST " Richard Henderson
2023-10-26 0:15 ` [PULL 73/94] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-26 0:15 ` [PULL 74/94] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-26 0:15 ` [PULL 75/94] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-26 0:15 ` [PULL 76/94] target/sparc: Move FSQRTq " Richard Henderson
2023-10-26 0:15 ` [PULL 77/94] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-26 0:15 ` [PULL 78/94] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-26 0:15 ` [PULL 79/94] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-26 0:15 ` [PULL 80/94] target/sparc: Move FSMULD " Richard Henderson
2023-10-26 0:15 ` [PULL 81/94] target/sparc: Move FDMULQ " Richard Henderson
2023-11-06 22:02 ` Mark Cave-Ayland
2023-11-07 4:49 ` Richard Henderson
2023-11-07 16:33 ` Mark Cave-Ayland
2023-10-26 0:15 ` [PULL 82/94] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-26 0:15 ` [PULL 83/94] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-26 0:15 ` [PULL 84/94] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-26 0:15 ` [PULL 85/94] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-26 0:15 ` [PULL 86/94] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-26 0:15 ` [PULL 87/94] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-26 0:15 ` [PULL 88/94] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-26 0:15 ` [PULL 89/94] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-26 0:15 ` [PULL 90/94] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-26 0:15 ` [PULL 91/94] target/sparc: Move FPCMP* " Richard Henderson
2023-10-26 0:15 ` [PULL 92/94] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-26 0:15 ` [PULL 93/94] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-26 0:15 ` [PULL 94/94] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-27 10:08 ` [PULL 00/94] target/sparc: Convert to decodetree Stefan Hajnoczi
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for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).