From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: [PULL 40/94] target/sparc: Move TADD, TSUB, MULS to decodetree
Date: Wed, 25 Oct 2023 17:14:48 -0700 [thread overview]
Message-ID: <20231026001542.1141412-70-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 7 ++++++
target/sparc/helper.c | 4 ----
target/sparc/translate.c | 48 ++++++++++++++++++---------------------
3 files changed, 29 insertions(+), 30 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 4415d03858..b35921aabb 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -32,6 +32,7 @@ CALL 01 i:s30
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
+@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
{
[
@@ -170,12 +171,18 @@ SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
+MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
+TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1
+TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1
+TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1
+TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1
+
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.
diff --git a/target/sparc/helper.c b/target/sparc/helper.c
index e25fdaeedd..2bcdc81d54 100644
--- a/target/sparc/helper.c
+++ b/target/sparc/helper.c
@@ -198,10 +198,8 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
}
/* Only modify the CC after any exceptions have been generated. */
- env->cc_op = CC_OP_TADDTV;
env->cc_src = src1;
env->cc_src2 = src2;
- env->cc_dst = dst;
return dst;
tag_overflow:
@@ -226,10 +224,8 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
}
/* Only modify the CC after any exceptions have been generated. */
- env->cc_op = CC_OP_TSUBTV;
env->cc_src = src1;
env->cc_src2 = src2;
- env->cc_dst = dst;
return dst;
tag_overflow:
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 1ebaaa1114..861c6e8f1e 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -730,6 +730,16 @@ static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
}
+static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_taddcctv(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_tsubcctv(dst, tcg_env, src1, src2);
+}
+
// 1
static void gen_op_eval_ba(TCGv dst)
{
@@ -4146,6 +4156,11 @@ TRANS(ADD, ALL, do_arith, a, CC_OP_ADD,
TRANS(SUB, ALL, do_arith, a, CC_OP_SUB,
tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc)
+TRANS(TADDcc, ALL, do_arith, a, CC_OP_TADD, NULL, NULL, gen_op_add_cc)
+TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc)
+TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcctv)
+TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcctv)
+
TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
@@ -4226,6 +4241,12 @@ static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a)
}
}
+static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
+{
+ update_psr(dc);
+ return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4653,36 +4674,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src2 = get_src2(dc, insn);
switch (xop) {
case 0x20: /* taddcc */
- gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
- dc->cc_op = CC_OP_TADD;
- break;
case 0x21: /* tsubcc */
- gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
- dc->cc_op = CC_OP_TSUB;
- break;
case 0x22: /* taddcctv */
- gen_helper_taddcctv(cpu_dst, tcg_env,
- cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, cpu_dst);
- dc->cc_op = CC_OP_TADDTV;
- break;
case 0x23: /* tsubcctv */
- gen_helper_tsubcctv(cpu_dst, tcg_env,
- cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, cpu_dst);
- dc->cc_op = CC_OP_TSUBTV;
- break;
case 0x24: /* mulscc */
- update_psr(dc);
- gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
- dc->cc_op = CC_OP_ADD;
- break;
+ goto illegal_insn; /* in decodetree */
#ifndef TARGET_SPARC64
case 0x25: /* sll */
if (IS_IMM) { /* immediate */
--
2.34.1
next prev parent reply other threads:[~2023-10-26 0:33 UTC|newest]
Thread overview: 135+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-26 0:13 [PULL 00/94] target/sparc: Convert to decodetree Richard Henderson
2023-10-26 0:13 ` [PULL 01/94] target/sparc: Clear may_lookup for npc == DYNAMIC_PC Richard Henderson
2023-10-26 0:13 ` [PATCH 01/29] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:13 ` [PULL 02/94] target/sparc: Implement check_align inline Richard Henderson
2023-10-26 0:13 ` [PATCH 02/29] tcg/optimize: Split out arg_is_const_val Richard Henderson
2023-10-26 0:13 ` [PULL 03/94] target/sparc: Avoid helper_raise_exception in helper_st_asi Richard Henderson
2023-10-26 0:13 ` [PATCH 03/29] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2023-10-26 0:13 ` [PULL 04/94] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-26 0:13 ` [PATCH 04/29] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2023-10-26 0:13 ` [PULL 05/94] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-26 0:13 ` [PATCH 05/29] tcg/optimize: Split out arg_new_constant Richard Henderson
2023-10-26 0:13 ` [PULL 06/94] target/sparc: Define features via cpu-feature.h.inc Richard Henderson
2023-10-26 0:13 ` [PATCH 06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-27 2:05 ` Paolo Bonzini
2023-10-26 0:13 ` [PULL 07/94] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties Richard Henderson
2023-10-26 0:13 ` [PATCH 07/29] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:13 ` [PULL 08/94] target/sparc: Remove sparcv7 cpu features Richard Henderson
2023-10-26 0:13 ` [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2023-10-27 4:44 ` Paolo Bonzini
2023-10-26 0:13 ` [PULL 09/94] target/sparc: Partition cpu features Richard Henderson
2023-10-26 0:13 ` [PATCH 09/29] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:13 ` [PULL 10/94] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-26 0:13 ` [PATCH 10/29] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2023-10-26 0:14 ` [PULL 11/94] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-26 0:14 ` [PATCH 11/29] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2023-10-26 0:14 ` [PULL 12/94] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi Richard Henderson
2023-10-26 0:14 ` [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 13/29] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 11:29 ` Paolo Bonzini
2023-10-26 16:07 ` Richard Henderson
2023-10-27 2:15 ` Paolo Bonzini
2023-10-26 0:14 ` [PULL 14/94] target/sparc: Move BPr to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 14/29] tcg/loongarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 16/94] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-26 0:14 ` [PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 17/94] target/sparc: Merge gen_fcond with only caller Richard Henderson
2023-10-26 0:14 ` [PATCH 17/29] tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson
2023-10-26 0:14 ` [PULL 18/94] target/sparc: Merge gen_branch_[an] with only caller Richard Henderson
2023-10-26 0:14 ` [PATCH 18/29] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2023-10-26 0:14 ` [PULL 19/94] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-26 0:14 ` [PATCH 19/29] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2023-10-26 0:14 ` [PULL 20/94] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 20/29] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 21/94] target/sparc: Move Tcc to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 21/29] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2023-10-26 0:14 ` [PULL 22/94] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree Richard Henderson
2023-11-03 19:07 ` Peter Maydell
2023-11-03 22:54 ` Richard Henderson
2023-10-26 0:14 ` [PATCH 22/29] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2023-10-26 0:14 ` [PULL 23/94] target/sparc: Move RDPSR, RDHPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 23/29] tcg/ppc: Create tcg_out_and_rc Richard Henderson
2023-10-26 0:14 ` [PULL 24/94] target/sparc: Move RDWIM, RDPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 24/29] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 25/94] target/sparc: Move RDTBR, FLUSHW to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 25/29] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PULL 26/94] target/sparc: Move WRASR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 26/29] tcg/tci: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-26 0:14 ` [PATCH 27/29] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2023-10-26 0:14 ` [PULL 27/94] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 28/29] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Richard Henderson
2023-10-26 0:14 ` [PULL 28/94] target/sparc: Move WRWIM, WRPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PATCH 29/29] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2023-10-26 0:14 ` [PULL 29/94] target/sparc: Move WRTBR, WRHPR to decodetree Richard Henderson
2023-10-26 0:14 ` [PULL 30/94] target/sparc: Remove cpu_wim Richard Henderson
2023-10-26 0:14 ` [PULL 31/94] target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr Richard Henderson
2023-10-26 0:14 ` [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver Richard Henderson
2023-10-26 0:14 ` [PULL 33/94] target/sparc: Move basic arithmetic to decodetree Richard Henderson
2023-10-26 0:14 ` [PULL 34/94] target/sparc: Move ADDC " Richard Henderson
2023-10-26 0:14 ` [PULL 35/94] target/sparc: Move MULX " Richard Henderson
2023-10-26 0:14 ` [PULL 36/94] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-26 0:14 ` [PULL 37/94] target/sparc: Move SUBC " Richard Henderson
2023-10-26 0:14 ` [PULL 38/94] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-26 0:14 ` [PULL 39/94] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-26 0:14 ` Richard Henderson [this message]
2023-10-26 0:14 ` [PULL 41/94] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-26 0:14 ` [PULL 42/94] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-26 0:14 ` [PULL 43/94] target/sparc: Move POPC " Richard Henderson
2023-10-26 0:14 ` [PULL 44/94] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-26 0:14 ` [PULL 45/94] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-26 0:14 ` [PULL 46/94] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-26 0:14 ` [PULL 47/94] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-26 0:14 ` [PULL 48/94] target/sparc: Split out resolve_asi Richard Henderson
2023-10-26 0:14 ` [PULL 49/94] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-26 0:14 ` [PULL 50/94] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-26 0:14 ` [PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-26 0:15 ` [PULL 52/94] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 53/94] target/sparc: Move asi " Richard Henderson
2023-10-26 0:15 ` [PULL 54/94] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-26 0:15 ` [PULL 55/94] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-26 0:15 ` [PULL 56/94] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-26 0:15 ` [PULL 57/94] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-26 0:15 ` [PULL 58/94] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-26 0:15 ` [PULL 59/94] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 60/94] target/sparc: Move asi " Richard Henderson
2023-10-26 0:15 ` [PULL 61/94] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-26 0:15 ` [PULL 62/94] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-26 0:15 ` [PULL 63/94] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 64/94] target/sparc: Move ARRAY* " Richard Henderson
2023-10-26 0:15 ` [PULL 65/94] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-26 0:15 ` [PULL 66/94] target/sparc: Move BMASK " Richard Henderson
2023-10-26 0:15 ` [PULL 67/94] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-26 0:15 ` [PULL 68/94] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-26 0:15 ` [PULL 69/94] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-26 0:15 ` [PULL 70/94] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-26 0:15 ` [PULL 71/94] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-26 0:15 ` [PULL 72/94] target/sparc: Move PDIST " Richard Henderson
2023-10-26 0:15 ` [PULL 73/94] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-26 0:15 ` [PULL 74/94] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-26 0:15 ` [PULL 75/94] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-26 0:15 ` [PULL 76/94] target/sparc: Move FSQRTq " Richard Henderson
2023-10-26 0:15 ` [PULL 77/94] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-26 0:15 ` [PULL 78/94] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-26 0:15 ` [PULL 79/94] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-26 0:15 ` [PULL 80/94] target/sparc: Move FSMULD " Richard Henderson
2023-10-26 0:15 ` [PULL 81/94] target/sparc: Move FDMULQ " Richard Henderson
2023-11-06 22:02 ` Mark Cave-Ayland
2023-11-07 4:49 ` Richard Henderson
2023-11-07 16:33 ` Mark Cave-Ayland
2023-10-26 0:15 ` [PULL 82/94] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-26 0:15 ` [PULL 83/94] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-26 0:15 ` [PULL 84/94] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-26 0:15 ` [PULL 85/94] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-26 0:15 ` [PULL 86/94] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-26 0:15 ` [PULL 87/94] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-26 0:15 ` [PULL 88/94] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-26 0:15 ` [PULL 89/94] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-26 0:15 ` [PULL 90/94] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-26 0:15 ` [PULL 91/94] target/sparc: Move FPCMP* " Richard Henderson
2023-10-26 0:15 ` [PULL 92/94] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-26 0:15 ` [PULL 93/94] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-26 0:15 ` [PULL 94/94] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-27 10:08 ` [PULL 00/94] target/sparc: Convert to decodetree Stefan Hajnoczi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231026001542.1141412-70-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=mark.cave-ayland@ilande.co.uk \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).