From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 2/6] tcg/mips: Always implement movcond
Date: Wed, 25 Oct 2023 21:14:00 -0700 [thread overview]
Message-ID: <20231026041404.1229328-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org>
Expand as branch over move if not supported in the ISA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.h | 4 ++--
tcg/mips/tcg-target.c.inc | 19 ++++++++++++++-----
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c0576f66d7..0a4083f0d9 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -154,7 +154,7 @@ extern bool use_mips32r2_instructions;
#endif
/* optional instructions detected at runtime */
-#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
@@ -169,7 +169,7 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
-#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index a5e6fe727b..f9b790ed8a 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1085,13 +1085,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
if (v2 != 0) {
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
}
- } else {
+ return;
+ }
+
+ /* This should be guaranteed via constraints */
+ tcg_debug_assert(v2 == ret);
+
+ if (use_movnz_instructions) {
MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
-
tcg_out_opc_reg(s, m_opc, ret, v1, c1);
-
- /* This should be guaranteed via constraints */
- tcg_debug_assert(v2 == ret);
+ } else {
+ /* Invert the condition in order to branch over the move. */
+ MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ;
+ tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2);
+ tcg_out_nop(s);
+ /* Open-code tcg_out_mov, without the nop-move check. */
+ tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO);
}
}
--
2.34.1
next prev parent reply other threads:[~2023-10-26 4:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-26 4:13 [PATCH 0/6] tcg: Always implement neg and movcond Richard Henderson
2023-10-26 4:13 ` [PATCH 1/6] tcg/mips: Split out tcg_out_setcond_int Richard Henderson
2023-10-26 4:14 ` Richard Henderson [this message]
2023-10-26 4:14 ` [PATCH 3/6] tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} Richard Henderson
2023-10-26 4:14 ` [PATCH 4/6] tcg/mips: Implement neg opcodes Richard Henderson
2023-10-26 4:14 ` [PATCH 5/6] tcg/loongarch64: " Richard Henderson
2023-10-26 4:14 ` [PATCH 6/6] tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} Richard Henderson
2023-10-26 4:20 ` [PATCH 0/6] tcg: Always implement neg and movcond Richard Henderson
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