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From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: [PATCH v2 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi
Date: Thu, 26 Oct 2023 23:18:19 +0800	[thread overview]
Message-ID: <20231026151828.754279-13-max.chou@sifive.com> (raw)
In-Reply-To: <20231026151828.754279-1-max.chou@sifive.com>

Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv.c | 14 +++++++++++++-
 disas/riscv.h |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index 8e89e1d1157..ec33e447f5b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst)
     return (inst << 34) >> 54;
 }
 
+static uint32_t operand_vzimm6(rv_inst inst)
+{
+    return ((inst << 37) >> 63) << 5 |
+        ((inst << 44) >> 59);
+}
+
 static uint32_t operand_bs(rv_inst inst)
 {
     return (inst << 32) >> 62;
@@ -4393,6 +4399,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
         dec->imm = operand_vimm(inst);
         dec->vm = operand_vm(inst);
         break;
+    case rv_codec_vror_vi:
+        dec->rd = operand_rd(inst);
+        dec->rs2 = operand_rs2(inst);
+        dec->imm = operand_vzimm6(inst);
+        dec->vm = operand_vm(inst);
+        break;
     case rv_codec_vsetvli:
         dec->rd = operand_rd(inst);
         dec->rs1 = operand_rs1(inst);
@@ -4677,7 +4689,7 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
             append(buf, tmp, buflen);
             break;
         case 'u':
-            snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
+            snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b111111));
             append(buf, tmp, buflen);
             break;
         case 'j':
diff --git a/disas/riscv.h b/disas/riscv.h
index b242d73b25e..19e5ed2ce63 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -152,6 +152,7 @@ typedef enum {
     rv_codec_v_i,
     rv_codec_vsetvli,
     rv_codec_vsetivli,
+    rv_codec_vror_vi,
     rv_codec_zcb_ext,
     rv_codec_zcb_mul,
     rv_codec_zcb_lb,
-- 
2.34.1



  parent reply	other threads:[~2023-10-26 15:22 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-26 15:18 [PATCH v2 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-26 15:18 ` [PATCH v2 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
2023-10-30 14:34   ` Daniel Henrique Barboza
2023-11-02  0:44   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 02/14] target/riscv: Expose Zvkt extension property Max Chou
2023-10-30 14:35   ` Daniel Henrique Barboza
2023-11-02  0:44   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 03/14] target/riscv: Add cfg property for Zvkb extension Max Chou
2023-10-30 14:49   ` Daniel Henrique Barboza
2023-11-02  0:45   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 04/14] target/riscv: Replace Zvbb checking by Zvkb Max Chou
2023-10-30 17:23   ` Daniel Henrique Barboza
2023-11-02  0:46   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 05/14] target/riscv: Expose Zvkb extension property Max Chou
2023-10-30 17:24   ` Daniel Henrique Barboza
2023-11-02  0:47   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
2023-10-30 17:28   ` Daniel Henrique Barboza
2023-11-02  0:49   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
2023-10-30 17:29   ` Daniel Henrique Barboza
2023-11-02  0:49   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou
2023-10-30 17:30   ` Daniel Henrique Barboza
2023-11-02  0:50   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Max Chou
2023-10-30 17:30   ` Daniel Henrique Barboza
2023-11-02  0:50   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
2023-10-30 17:33   ` Daniel Henrique Barboza
2023-11-02  0:51   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
2023-11-02  0:52   ` Alistair Francis
2023-10-26 15:18 ` Max Chou [this message]
2023-11-02  0:57   ` [PATCH v2 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Alistair Francis
2023-10-26 15:18 ` [PATCH v2 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
2023-11-02  0:59   ` Alistair Francis
2023-10-26 15:18 ` [PATCH v2 14/14] disas/riscv: Replace TABs with space Max Chou
2023-11-02  1:00   ` Alistair Francis
2023-11-02  1:38 ` [PATCH v2 00/14] Update RISC-V vector crypto to ratified v1.0.0 Alistair Francis

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