From: Thomas Huth <thuth@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org,
Sebastian Mitterle <smitterl@redhat.com>,
Ilya Leoshkevich <iii@linux.ibm.com>,
Laurent Vivier <laurent@vivier.eu>,
Thomas Huth <thuth@redhat.com>
Subject: [risu PATCH 2/2] s390x.risu: Add some instructions with a length of 48 bits
Date: Fri, 27 Oct 2023 12:04:41 +0200 [thread overview]
Message-ID: <20231027100441.375223-3-thuth@redhat.com> (raw)
In-Reply-To: <20231027100441.375223-1-thuth@redhat.com>
Now that risugen can handle instructions with a length > 32 bit,
we can test some instructions with the length of 48-bit, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
s390x.risu | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/s390x.risu b/s390x.risu
index 1661be6..b70678a 100644
--- a/s390x.risu
+++ b/s390x.risu
@@ -27,6 +27,19 @@ ARK STFLE45 10111001 11111000 r3:4 0000 r1:4 r2:4
AGRK STFLE45 10111001 11101000 r3:4 0000 r1:4 r2:4
+# format:RIL-a Add immediate (32 bit)
+AFI EI 11000010 r1:4 1001 i2a:16 i2b:16
+
+# format:RIL-a Add immediate (64 bit)
+AGFI EI 11000010 r1:4 1000 i2a:16 i2b:16
+
+# format:RIE-d Add Immediate (32 bit, distinct operand)
+AHIK STFLE35 11101100 r1:4 r3:4 i2:16 00000000 11011000
+
+# format:RIE-d Add Immediate (64 bit, distinct operand)
+AGHIK STFLE35 11101100 r1:4 r3:4 i2:16 00000000 11011001
+
+
# format:RRE Add Halfword Immediate (32 bit)
AHI Z 10100111 r1:4 1010 i2:16
@@ -44,6 +57,13 @@ ALGR Z 10111001 00001010 00000000 r1:4 r2:4
ALGFR Z 10111001 00011010 00000000 r1:4 r2:4
+# format:RIL-a Insert Immediate (32 bit to upper word)
+IIHF EI 11000000 r1:4 1000 i2a:16 i2b:16
+
+# format:RIL-a Insert Immediate (32 bit to upper word)
+IILF EI 11000000 r1:4 1001 i2a:16 i2b:16
+
+
# format:RRF-c Population Count
POPCNT STFLE45 10111001 11100001 m3:4 0000 r1:4 r2:4
--
2.41.0
prev parent reply other threads:[~2023-10-27 10:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-27 10:04 [risu PATCH 0/2] Add support for instructions with length > 32 bit Thomas Huth
2023-10-27 10:04 ` [risu PATCH 1/2] risugen: allow " Thomas Huth
2023-10-31 15:34 ` Peter Maydell
2023-10-27 10:04 ` Thomas Huth [this message]
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