From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support
Date: Sat, 28 Oct 2023 12:43:07 +0200 [thread overview]
Message-ID: <20231028-588cc5e3969c1962985c2f69@orel> (raw)
In-Reply-To: <20231028085427.707060-7-dbarboza@ventanamicro.com>
On Sat, Oct 28, 2023 at 05:54:21AM -0300, Daniel Henrique Barboza wrote:
> The TCG emulation implements all the extensions described in the
> RVA22U64 profile, both mandatory and optional. The mandatory extensions
> will be enabled via the profile flag. We'll leave the optional
> extensions to be enabled by hand.
>
> Given that this is the first profile we're implementing in TCG we'll
> need some ground work first:
>
> - all profiles declared in riscv_profiles[] will be exposed to users.
> TCG is the main accelerator we're considering when adding profile
> support in QEMU, so for now it's safe to assume that all profiles in
> riscv_profiles[] will be relevant to TCG;
>
> - we'll not support user profile settings for vendor CPUs. The flags
> will still be exposed but users won't be able to change them. The idea
> is that vendor CPUs in the future can enable profiles internally in
> their cpu_init() functions, showing to the external world that the CPU
> supports a certain profile. But users won't be able to enable/disable
> it;
>
> - Setting a profile to 'true' means 'enable all mandatory extensions of
> this profile, setting it to 'false' means 'do not enable all mandatory
> extensions for this profile'.
While this definition of profile=off looks appealing at first, it's really
just saying 'do not do anything', which means it's limiting the potential
of the property. But, I'll stop talking about this now, as I have another
design suggestion instead:
Since profiles are like G, and other shorthand extensions (just without an
official shorthand extension name), then I believe they should behave like
shorthand extensions. Also, since shorthand extensions can be derived from
their parts, then I think shorthand extensions should behave like
synthetic extensions. For example, zic64b starts 'false', but, at realize
time, if all its conditions are present, then it turns 'true'. Shorthand
extensions should be able to do that too by detecting that each of the
extensions they represent is present.
So, I think we should automatically turn G and profiles (and future
shorthand extensions) on when all their respective extensions are present.
Thanks,
drew
next prev parent reply other threads:[~2023-10-28 10:44 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-28 8:54 [PATCH v6 00/12] RVA22U64 profile support Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 01/12] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-10-28 9:49 ` Andrew Jones
2023-10-28 16:49 ` Daniel Henrique Barboza
2023-10-30 11:49 ` Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 02/12] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-10-28 9:54 ` Andrew Jones
2023-10-28 8:54 ` [PATCH v6 03/12] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-10-28 10:02 ` Andrew Jones
2023-10-28 8:54 ` [PATCH v6 04/12] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 05/12] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-28 10:43 ` Andrew Jones [this message]
2023-10-30 3:47 ` Alistair Francis
2023-10-30 13:28 ` Daniel Henrique Barboza
2023-10-30 17:18 ` Daniel Henrique Barboza
2023-11-02 3:00 ` Alistair Francis
2023-11-02 9:52 ` Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 07/12] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 08/12] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 09/12] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-30 3:48 ` Alistair Francis
2023-10-28 8:54 ` [PATCH v6 10/12] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-28 8:54 ` [PATCH v6 11/12] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-30 3:50 ` Alistair Francis
2023-10-28 8:54 ` [PATCH v6 12/12] target/riscv/tcg: warn if profile exts are disabled Daniel Henrique Barboza
2023-10-30 4:01 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231028-588cc5e3969c1962985c2f69@orel \
--to=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).