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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id k19-20020a508ad3000000b0053e0395059csm2708705edk.21.2023.10.28.03.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 03:43:08 -0700 (PDT) Date: Sat, 28 Oct 2023 12:43:07 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support Message-ID: <20231028-588cc5e3969c1962985c2f69@orel> References: <20231028085427.707060-1-dbarboza@ventanamicro.com> <20231028085427.707060-7-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231028085427.707060-7-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Oct 28, 2023 at 05:54:21AM -0300, Daniel Henrique Barboza wrote: > The TCG emulation implements all the extensions described in the > RVA22U64 profile, both mandatory and optional. The mandatory extensions > will be enabled via the profile flag. We'll leave the optional > extensions to be enabled by hand. > > Given that this is the first profile we're implementing in TCG we'll > need some ground work first: > > - all profiles declared in riscv_profiles[] will be exposed to users. > TCG is the main accelerator we're considering when adding profile > support in QEMU, so for now it's safe to assume that all profiles in > riscv_profiles[] will be relevant to TCG; > > - we'll not support user profile settings for vendor CPUs. The flags > will still be exposed but users won't be able to change them. The idea > is that vendor CPUs in the future can enable profiles internally in > their cpu_init() functions, showing to the external world that the CPU > supports a certain profile. But users won't be able to enable/disable > it; > > - Setting a profile to 'true' means 'enable all mandatory extensions of > this profile, setting it to 'false' means 'do not enable all mandatory > extensions for this profile'. While this definition of profile=off looks appealing at first, it's really just saying 'do not do anything', which means it's limiting the potential of the property. But, I'll stop talking about this now, as I have another design suggestion instead: Since profiles are like G, and other shorthand extensions (just without an official shorthand extension name), then I believe they should behave like shorthand extensions. Also, since shorthand extensions can be derived from their parts, then I think shorthand extensions should behave like synthetic extensions. For example, zic64b starts 'false', but, at realize time, if all its conditions are present, then it turns 'true'. Shorthand extensions should be able to do that too by detecting that each of the extensions they represent is present. So, I think we should automatically turn G and profiles (and future shorthand extensions) on when all their respective extensions are present. Thanks, drew