From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org, pbonzini@redhat.com
Subject: [PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ
Date: Sat, 28 Oct 2023 12:44:56 -0700 [thread overview]
Message-ID: <20231028194522.245170-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231028194522.245170-1-richard.henderson@linaro.org>
Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 100 ++++++++++++++++++++++++++++-------
1 file changed, 81 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 70df250c04..55225313ad 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -105,6 +105,18 @@ static bool reloc_pc19(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
return false;
}
+static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+ ptrdiff_t offset = target - src_rx;
+
+ if (offset == sextract64(offset, 0, 14)) {
+ *src_rw = deposit32(*src_rw, 5, 14, offset);
+ return true;
+ }
+ return false;
+}
+
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
@@ -115,6 +127,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return reloc_pc26(code_ptr, (const tcg_insn_unit *)value);
case R_AARCH64_CONDBR19:
return reloc_pc19(code_ptr, (const tcg_insn_unit *)value);
+ case R_AARCH64_TSTBR14:
+ return reloc_pc14(code_ptr, (const tcg_insn_unit *)value);
default:
g_assert_not_reached();
}
@@ -380,6 +394,10 @@ typedef enum {
/* Conditional branch (immediate). */
I3202_B_C = 0x54000000,
+ /* Test and branch (immediate). */
+ I3205_TBZ = 0x36000000,
+ I3205_TBNZ = 0x37000000,
+
/* Unconditional branch (immediate). */
I3206_B = 0x14000000,
I3206_BL = 0x94000000,
@@ -660,6 +678,14 @@ static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn,
tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5);
}
+static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn,
+ TCGReg rt, int imm6, int imm14)
+{
+ insn |= (imm6 & 0x20) << (31 - 5);
+ insn |= (imm6 & 0x1f) << 19;
+ tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt);
+}
+
static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26)
{
tcg_out32(s, insn | (imm26 & 0x03ffffff));
@@ -1415,30 +1441,66 @@ static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l)
static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
TCGArg b, bool b_const, TCGLabel *l)
{
- intptr_t offset;
- bool need_cmp;
+ int tbit = -1;
+ bool need_cmp = true;
- if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) {
- need_cmp = false;
- } else {
- need_cmp = true;
- tcg_out_cmp(s, ext, c, a, b, b_const);
- }
-
- if (!l->has_value) {
- tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
- offset = tcg_in32(s) >> 5;
- } else {
- offset = tcg_pcrel_diff(s, l->u.value_ptr) >> 2;
- tcg_debug_assert(offset == sextract64(offset, 0, 19));
+ switch (c) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ if (b_const && b == 0) {
+ need_cmp = false;
+ }
+ break;
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ if (b_const && b == 0) {
+ c = (c == TCG_COND_LT ? TCG_COND_TSTNE : TCG_COND_TSTEQ);
+ tbit = ext ? 63 : 31;
+ need_cmp = false;
+ }
+ break;
+ case TCG_COND_TSTEQ:
+ case TCG_COND_TSTNE:
+ if (b_const && is_power_of_2(b)) {
+ tbit = ctz64(b);
+ need_cmp = false;
+ }
+ break;
+ default:
+ break;
}
if (need_cmp) {
- tcg_out_insn(s, 3202, B_C, c, offset);
- } else if (c == TCG_COND_EQ) {
- tcg_out_insn(s, 3201, CBZ, ext, a, offset);
+ tcg_out_cmp(s, ext, c, a, b, b_const);
+ tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
+ tcg_out_insn(s, 3202, B_C, c, 0);
+ return;
+ }
+
+ if (tbit >= 0) {
+ tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0);
+ switch (c) {
+ case TCG_COND_TSTEQ:
+ tcg_out_insn(s, 3205, TBZ, a, tbit, 0);
+ break;
+ case TCG_COND_TSTNE:
+ tcg_out_insn(s, 3205, TBNZ, a, tbit, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
} else {
- tcg_out_insn(s, 3201, CBNZ, ext, a, offset);
+ tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
+ switch (c) {
+ case TCG_COND_EQ:
+ tcg_out_insn(s, 3201, CBZ, ext, a, 0);
+ break;
+ case TCG_COND_NE:
+ tcg_out_insn(s, 3201, CBNZ, ext, a, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
}
--
2.34.1
next prev parent reply other threads:[~2023-10-28 19:48 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-28 19:44 [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:44 ` [PATCH v2 01/35] " Richard Henderson
2023-11-06 15:26 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 02/35] tcg/optimize: Split out arg_is_const_val Richard Henderson
2023-11-06 15:28 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 03/35] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2023-11-06 15:33 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 04/35] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2023-11-06 21:27 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 05/35] tcg/optimize: Split out arg_new_constant Richard Henderson
2023-11-06 15:34 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 06/35] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-06 21:20 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 07/35] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2023-11-06 18:47 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 08/35] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:44 ` Richard Henderson [this message]
2023-10-28 19:44 ` [PATCH v2 10/35] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2023-10-28 19:44 ` [PATCH v2 11/35] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 14:52 ` [PATCH v2 11/35 1/2] tcg/arm: Factor tcg_out_cmp() out Philippe Mathieu-Daudé
2023-11-08 14:52 ` [PATCH v2 11/35 2/2] tcg/arm: Support TCG_COND_TST{EQ,NE} Philippe Mathieu-Daudé
2023-11-08 17:59 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 12/35] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2023-11-06 20:55 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 13/35] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2023-11-06 19:46 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 14/35] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 18:16 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 15/35] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2023-10-28 19:45 ` [PATCH v2 16/35] tcg/loongarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-17 7:48 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 17/35] tcg/mips: " Richard Henderson
2023-11-17 7:46 ` Philippe Mathieu-Daudé
2023-11-17 16:36 ` Richard Henderson
2023-12-13 14:06 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 18/35] tcg/riscv: " Richard Henderson
2023-11-06 20:59 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 19/35] tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson
2023-11-06 15:05 ` Philippe Mathieu-Daudé
2023-11-06 18:07 ` Richard Henderson
2023-10-28 19:45 ` [PATCH v2 20/35] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2023-11-06 21:02 ` Philippe Mathieu-Daudé
2023-11-08 20:57 ` Richard Henderson
2023-11-09 8:35 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 21/35] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2023-11-09 11:29 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 22/35] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-06 21:07 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 23/35] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2023-11-06 18:54 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 24/35] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2023-10-28 19:45 ` [PATCH v2 25/35] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2023-11-06 21:08 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 26/35] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2023-10-28 19:45 ` [PATCH v2 27/35] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 20:40 ` Philippe Mathieu-Daudé
2023-11-08 21:27 ` Richard Henderson
2023-11-09 8:42 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 28/35] tcg/s390x: Split constraint A into J+U Richard Henderson
2023-10-28 19:45 ` [PATCH v2 29/35] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2023-10-28 19:45 ` [PATCH v2 30/35] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:45 ` [PATCH v2 31/35] tcg/tci: " Richard Henderson
2023-11-06 18:48 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2023-11-08 20:52 ` [PATCH v2 32/35 1/2] target/alpha: Pass immediate value to gen_bcond_internal() Philippe Mathieu-Daudé
2023-11-08 20:55 ` Philippe Mathieu-Daudé
2023-11-08 20:52 ` [PATCH v2 32/35 2/2] target/alpha: Use TCG_COND_TST{EQ, NE} for BLB{C, S} Philippe Mathieu-Daudé
2023-11-08 20:56 ` [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} Richard Henderson
2023-11-08 20:54 ` [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 34/35] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2023-11-08 21:03 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 35/35] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond Richard Henderson
2023-11-02 22:17 ` [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-06 17:43 ` Paolo Bonzini
2024-01-08 21:45 ` Richard Henderson
2024-01-08 22:55 ` Paolo Bonzini
2024-01-09 8:36 ` Richard Henderson
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