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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org, pbonzini@redhat.com
Subject: [PATCH v2 28/35] tcg/s390x: Split constraint A into J+U
Date: Sat, 28 Oct 2023 12:45:15 -0700	[thread overview]
Message-ID: <20231028194522.245170-29-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231028194522.245170-1-richard.henderson@linaro.org>

Signed 33-bit == signed 32-bit + unsigned 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target-con-set.h |  8 ++++----
 tcg/s390x/tcg-target-con-str.h |  2 +-
 tcg/s390x/tcg-target.c.inc     | 36 +++++++++++++++++-----------------
 3 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 9a42037499..665851d84a 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -15,7 +15,7 @@
 C_O0_I1(r)
 C_O0_I2(r, r)
 C_O0_I2(r, ri)
-C_O0_I2(r, rA)
+C_O0_I2(r, rJU)
 C_O0_I2(v, r)
 C_O0_I3(o, m, r)
 C_O1_I1(r, r)
@@ -27,7 +27,7 @@ C_O1_I2(r, 0, rI)
 C_O1_I2(r, 0, rJ)
 C_O1_I2(r, r, r)
 C_O1_I2(r, r, ri)
-C_O1_I2(r, r, rA)
+C_O1_I2(r, r, rJU)
 C_O1_I2(r, r, rI)
 C_O1_I2(r, r, rJ)
 C_O1_I2(r, r, rK)
@@ -39,10 +39,10 @@ C_O1_I2(v, v, r)
 C_O1_I2(v, v, v)
 C_O1_I3(v, v, v, v)
 C_O1_I4(r, r, ri, rI, r)
-C_O1_I4(r, r, rA, rI, r)
+C_O1_I4(r, r, rJU, rI, r)
 C_O2_I1(o, m, r)
 C_O2_I2(o, m, 0, r)
 C_O2_I2(o, m, r, r)
 C_O2_I3(o, m, 0, 1, r)
 C_N1_O1_I4(r, r, 0, 1, ri, r)
-C_N1_O1_I4(r, r, 0, 1, rA, r)
+C_N1_O1_I4(r, r, 0, 1, rJU, r)
diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h
index 25675b449e..9d2cb775dc 100644
--- a/tcg/s390x/tcg-target-con-str.h
+++ b/tcg/s390x/tcg-target-con-str.h
@@ -16,10 +16,10 @@ REGS('o', 0xaaaa) /* odd numbered general regs */
  * Define constraint letters for constants:
  * CONST(letter, TCG_CT_CONST_* bit set)
  */
-CONST('A', TCG_CT_CONST_S33)
 CONST('I', TCG_CT_CONST_S16)
 CONST('J', TCG_CT_CONST_S32)
 CONST('K', TCG_CT_CONST_P32)
 CONST('N', TCG_CT_CONST_INV)
 CONST('R', TCG_CT_CONST_INVRISBG)
+CONST('U', TCG_CT_CONST_U32)
 CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 08fe00a392..a317ccd3a5 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -30,7 +30,7 @@
 
 #define TCG_CT_CONST_S16        (1 << 8)
 #define TCG_CT_CONST_S32        (1 << 9)
-#define TCG_CT_CONST_S33        (1 << 10)
+#define TCG_CT_CONST_U32        (1 << 10)
 #define TCG_CT_CONST_ZERO       (1 << 11)
 #define TCG_CT_CONST_P32        (1 << 12)
 #define TCG_CT_CONST_INV        (1 << 13)
@@ -542,22 +542,23 @@ static bool tcg_target_const_match(int64_t val, int ct,
                                    TCGType type, TCGCond cond, int vece)
 {
     if (ct & TCG_CT_CONST) {
-        return 1;
+        return true;
     }
-
     if (type == TCG_TYPE_I32) {
         val = (int32_t)val;
     }
 
-    /* The following are mutually exclusive.  */
-    if (ct & TCG_CT_CONST_S16) {
-        return val == (int16_t)val;
-    } else if (ct & TCG_CT_CONST_S32) {
-        return val == (int32_t)val;
-    } else if (ct & TCG_CT_CONST_S33) {
-        return val >= -0xffffffffll && val <= 0xffffffffll;
-    } else if (ct & TCG_CT_CONST_ZERO) {
-        return val == 0;
+    if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+        return true;
     }
 
     if (ct & TCG_CT_CONST_INV) {
@@ -573,8 +574,7 @@ static bool tcg_target_const_match(int64_t val, int ct,
     if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) {
         return true;
     }
-
-    return 0;
+    return false;
 }
 
 /* Emit instructions according to the given instruction format.  */
@@ -3137,7 +3137,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
         return C_O1_I2(r, r, ri);
     case INDEX_op_setcond_i64:
     case INDEX_op_negsetcond_i64:
-        return C_O1_I2(r, r, rA);
+        return C_O1_I2(r, r, rJU);
 
     case INDEX_op_clz_i64:
         return C_O1_I2(r, r, rI);
@@ -3187,7 +3187,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_brcond_i32:
         return C_O0_I2(r, ri);
     case INDEX_op_brcond_i64:
-        return C_O0_I2(r, rA);
+        return C_O0_I2(r, rJU);
 
     case INDEX_op_bswap16_i32:
     case INDEX_op_bswap16_i64:
@@ -3240,7 +3240,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_movcond_i32:
         return C_O1_I4(r, r, ri, rI, r);
     case INDEX_op_movcond_i64:
-        return C_O1_I4(r, r, rA, rI, r);
+        return C_O1_I4(r, r, rJU, rI, r);
 
     case INDEX_op_div2_i32:
     case INDEX_op_div2_i64:
@@ -3259,7 +3259,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_add2_i64:
     case INDEX_op_sub2_i64:
-        return C_N1_O1_I4(r, r, 0, 1, rA, r);
+        return C_N1_O1_I4(r, r, 0, 1, rJU, r);
 
     case INDEX_op_st_vec:
         return C_O0_I2(v, r);
-- 
2.34.1



  parent reply	other threads:[~2023-10-28 19:47 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-28 19:44 [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:44 ` [PATCH v2 01/35] " Richard Henderson
2023-11-06 15:26   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 02/35] tcg/optimize: Split out arg_is_const_val Richard Henderson
2023-11-06 15:28   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 03/35] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2023-11-06 15:33   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 04/35] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2023-11-06 21:27   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 05/35] tcg/optimize: Split out arg_new_constant Richard Henderson
2023-11-06 15:34   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 06/35] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-06 21:20   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 07/35] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2023-11-06 18:47   ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 08/35] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:44 ` [PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2023-10-28 19:44 ` [PATCH v2 10/35] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2023-10-28 19:44 ` [PATCH v2 11/35] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 14:52   ` [PATCH v2 11/35 1/2] tcg/arm: Factor tcg_out_cmp() out Philippe Mathieu-Daudé
2023-11-08 14:52   ` [PATCH v2 11/35 2/2] tcg/arm: Support TCG_COND_TST{EQ,NE} Philippe Mathieu-Daudé
2023-11-08 17:59     ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 12/35] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2023-11-06 20:55   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 13/35] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2023-11-06 19:46   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 14/35] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 18:16   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 15/35] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2023-10-28 19:45 ` [PATCH v2 16/35] tcg/loongarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-17  7:48   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 17/35] tcg/mips: " Richard Henderson
2023-11-17  7:46   ` Philippe Mathieu-Daudé
2023-11-17 16:36     ` Richard Henderson
2023-12-13 14:06       ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 18/35] tcg/riscv: " Richard Henderson
2023-11-06 20:59   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 19/35] tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson
2023-11-06 15:05   ` Philippe Mathieu-Daudé
2023-11-06 18:07     ` Richard Henderson
2023-10-28 19:45 ` [PATCH v2 20/35] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2023-11-06 21:02   ` Philippe Mathieu-Daudé
2023-11-08 20:57     ` Richard Henderson
2023-11-09  8:35       ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 21/35] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2023-11-09 11:29   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 22/35] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-06 21:07   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 23/35] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2023-11-06 18:54   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 24/35] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2023-10-28 19:45 ` [PATCH v2 25/35] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2023-11-06 21:08   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 26/35] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2023-10-28 19:45 ` [PATCH v2 27/35] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 20:40   ` Philippe Mathieu-Daudé
2023-11-08 21:27     ` Richard Henderson
2023-11-09  8:42   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` Richard Henderson [this message]
2023-10-28 19:45 ` [PATCH v2 29/35] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2023-10-28 19:45 ` [PATCH v2 30/35] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:45 ` [PATCH v2 31/35] tcg/tci: " Richard Henderson
2023-11-06 18:48   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2023-11-08 20:52   ` [PATCH v2 32/35 1/2] target/alpha: Pass immediate value to gen_bcond_internal() Philippe Mathieu-Daudé
2023-11-08 20:55     ` Philippe Mathieu-Daudé
2023-11-08 20:52   ` [PATCH v2 32/35 2/2] target/alpha: Use TCG_COND_TST{EQ, NE} for BLB{C, S} Philippe Mathieu-Daudé
2023-11-08 20:56   ` [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} Richard Henderson
2023-11-08 20:54   ` [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 34/35] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2023-11-08 21:03   ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 35/35] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond Richard Henderson
2023-11-02 22:17 ` [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-06 17:43 ` Paolo Bonzini
2024-01-08 21:45   ` Richard Henderson
2024-01-08 22:55     ` Paolo Bonzini
2024-01-09  8:36       ` Richard Henderson

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