From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org, pbonzini@redhat.com
Subject: [PATCH v2 35/35] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond
Date: Sat, 28 Oct 2023 12:45:22 -0700 [thread overview]
Message-ID: <20231028194522.245170-36-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231028194522.245170-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 74 ++++++++++++++++++-----------------------
1 file changed, 33 insertions(+), 41 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 4a0b0b2703..f30b92f2d4 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5129,46 +5129,44 @@ undef:
static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv fpsr;
+ int imm = 0;
- c->v2 = tcg_constant_i32(0);
/* TODO: Raise BSUN exception. */
fpsr = tcg_temp_new();
gen_load_fcr(s, fpsr, M68K_FPSR);
+ c->v1 = fpsr;
+
switch (cond) {
case 0: /* False */
case 16: /* Signaling False */
- c->v1 = c->v2;
c->tcond = TCG_COND_NEVER;
break;
case 1: /* EQual Z */
case 17: /* Signaling EQual Z */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTNE;
break;
case 2: /* Ordered Greater Than !(A || Z || N) */
case 18: /* Greater Than !(A || Z || N) */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr,
- FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 3: /* Ordered Greater than or Equal Z || !(A || N) */
case 19: /* Greater than or Equal Z || !(A || N) */
c->v1 = tcg_temp_new();
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
- tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
tcg_gen_or_i32(c->v1, c->v1, fpsr);
tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 4: /* Ordered Less Than !(!N || A || Z); */
case 20: /* Less Than !(!N || A || Z); */
c->v1 = tcg_temp_new();
tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
- tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 5: /* Ordered Less than or Equal Z || (N && !A) */
case 21: /* Less than or Equal Z || (N && !A) */
@@ -5176,49 +5174,45 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
tcg_gen_andc_i32(c->v1, fpsr, c->v1);
- tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 6: /* Ordered Greater or Less than !(A || Z) */
case 22: /* Greater or Less than !(A || Z) */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_A | FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 7: /* Ordered !A */
case 23: /* Greater, Less or Equal !A */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_A;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 8: /* Unordered A */
case 24: /* Not Greater, Less or Equal A */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A;
+ c->tcond = TCG_COND_TSTNE;
break;
case 9: /* Unordered or Equal A || Z */
case 25: /* Not Greater or Less then A || Z */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTNE;
break;
case 10: /* Unordered or Greater Than A || !(N || Z)) */
case 26: /* Not Less or Equal A || !(N || Z)) */
c->v1 = tcg_temp_new();
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
- tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
tcg_gen_or_i32(c->v1, c->v1, fpsr);
tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 11: /* Unordered or Greater or Equal A || Z || !N */
case 27: /* Not Less Than A || Z || !N */
c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
- tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
+ imm = FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 12: /* Unordered or Less Than A || (N && !Z) */
case 28: /* Not Greater than or Equal A || (N && !Z) */
@@ -5226,27 +5220,25 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
tcg_gen_andc_i32(c->v1, fpsr, c->v1);
- tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 13: /* Unordered or Less or Equal A || Z || N */
case 29: /* Not Greater Than A || Z || N */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 14: /* Not Equal !Z */
case 30: /* Signaling Not Equal !Z */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 15: /* True */
case 31: /* Signaling True */
- c->v1 = c->v2;
c->tcond = TCG_COND_ALWAYS;
break;
}
+ c->v2 = tcg_constant_i32(imm);
}
static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
--
2.34.1
next prev parent reply other threads:[~2023-10-28 19:50 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-28 19:44 [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:44 ` [PATCH v2 01/35] " Richard Henderson
2023-11-06 15:26 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 02/35] tcg/optimize: Split out arg_is_const_val Richard Henderson
2023-11-06 15:28 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 03/35] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2023-11-06 15:33 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 04/35] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2023-11-06 21:27 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 05/35] tcg/optimize: Split out arg_new_constant Richard Henderson
2023-11-06 15:34 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 06/35] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-06 21:20 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 07/35] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2023-11-06 18:47 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 08/35] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:44 ` [PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2023-10-28 19:44 ` [PATCH v2 10/35] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2023-10-28 19:44 ` [PATCH v2 11/35] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 14:52 ` [PATCH v2 11/35 1/2] tcg/arm: Factor tcg_out_cmp() out Philippe Mathieu-Daudé
2023-11-08 14:52 ` [PATCH v2 11/35 2/2] tcg/arm: Support TCG_COND_TST{EQ,NE} Philippe Mathieu-Daudé
2023-11-08 17:59 ` Philippe Mathieu-Daudé
2023-10-28 19:44 ` [PATCH v2 12/35] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2023-11-06 20:55 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 13/35] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2023-11-06 19:46 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 14/35] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 18:16 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 15/35] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2023-10-28 19:45 ` [PATCH v2 16/35] tcg/loongarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-17 7:48 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 17/35] tcg/mips: " Richard Henderson
2023-11-17 7:46 ` Philippe Mathieu-Daudé
2023-11-17 16:36 ` Richard Henderson
2023-12-13 14:06 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 18/35] tcg/riscv: " Richard Henderson
2023-11-06 20:59 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 19/35] tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson
2023-11-06 15:05 ` Philippe Mathieu-Daudé
2023-11-06 18:07 ` Richard Henderson
2023-10-28 19:45 ` [PATCH v2 20/35] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2023-11-06 21:02 ` Philippe Mathieu-Daudé
2023-11-08 20:57 ` Richard Henderson
2023-11-09 8:35 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 21/35] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2023-11-09 11:29 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 22/35] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-06 21:07 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 23/35] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2023-11-06 18:54 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 24/35] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2023-10-28 19:45 ` [PATCH v2 25/35] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2023-11-06 21:08 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 26/35] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2023-10-28 19:45 ` [PATCH v2 27/35] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-11-08 20:40 ` Philippe Mathieu-Daudé
2023-11-08 21:27 ` Richard Henderson
2023-11-09 8:42 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 28/35] tcg/s390x: Split constraint A into J+U Richard Henderson
2023-10-28 19:45 ` [PATCH v2 29/35] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2023-10-28 19:45 ` [PATCH v2 30/35] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2023-10-28 19:45 ` [PATCH v2 31/35] tcg/tci: " Richard Henderson
2023-11-06 18:48 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2023-11-08 20:52 ` [PATCH v2 32/35 1/2] target/alpha: Pass immediate value to gen_bcond_internal() Philippe Mathieu-Daudé
2023-11-08 20:55 ` Philippe Mathieu-Daudé
2023-11-08 20:52 ` [PATCH v2 32/35 2/2] target/alpha: Use TCG_COND_TST{EQ, NE} for BLB{C, S} Philippe Mathieu-Daudé
2023-11-08 20:56 ` [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} Richard Henderson
2023-11-08 20:54 ` [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Philippe Mathieu-Daudé
2023-10-28 19:45 ` [PATCH v2 34/35] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2023-11-08 21:03 ` Philippe Mathieu-Daudé
2023-10-28 19:45 ` Richard Henderson [this message]
2023-11-02 22:17 ` [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-06 17:43 ` Paolo Bonzini
2024-01-08 21:45 ` Richard Henderson
2024-01-08 22:55 ` Paolo Bonzini
2024-01-09 8:36 ` Richard Henderson
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