* [PATCH] target/arm: Fix SVE STR increment
@ 2023-10-30 19:03 Richard Henderson
2023-10-30 19:29 ` Alex Bennée
2023-10-31 10:52 ` Peter Maydell
0 siblings, 2 replies; 4+ messages in thread
From: Richard Henderson @ 2023-10-30 19:03 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, qemu-stable
The previous change missed updating one of the increments.
Cc: qemu-stable@nongnu.org
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-sve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 7b39962f20..fc4220114d 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4294,7 +4294,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t16 = tcg_temp_new_i128();
- for (i = 0; i < len_align; i += 8) {
+ for (i = 0; i < len_align; i += 16) {
tcg_gen_ld_i64(t0, base, vofs + i);
tcg_gen_ld_i64(t1, base, vofs + i + 8);
tcg_gen_concat_i64_i128(t16, t0, t1);
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/arm: Fix SVE STR increment
2023-10-30 19:03 [PATCH] target/arm: Fix SVE STR increment Richard Henderson
@ 2023-10-30 19:29 ` Alex Bennée
2023-10-31 10:52 ` Peter Maydell
1 sibling, 0 replies; 4+ messages in thread
From: Alex Bennée @ 2023-10-30 19:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm, qemu-stable
Richard Henderson <richard.henderson@linaro.org> writes:
> The previous change missed updating one of the increments.
>
> Cc: qemu-stable@nongnu.org
> Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/arm: Fix SVE STR increment
2023-10-30 19:03 [PATCH] target/arm: Fix SVE STR increment Richard Henderson
2023-10-30 19:29 ` Alex Bennée
@ 2023-10-31 10:52 ` Peter Maydell
2023-10-31 14:08 ` Richard Henderson
1 sibling, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2023-10-31 10:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm, qemu-stable
On Mon, 30 Oct 2023 at 19:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The previous change missed updating one of the increments.
>
> Cc: qemu-stable@nongnu.org
> Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-sve.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
> index 7b39962f20..fc4220114d 100644
> --- a/target/arm/tcg/translate-sve.c
> +++ b/target/arm/tcg/translate-sve.c
> @@ -4294,7 +4294,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
> t0 = tcg_temp_new_i64();
> t1 = tcg_temp_new_i64();
> t16 = tcg_temp_new_i128();
> - for (i = 0; i < len_align; i += 8) {
> + for (i = 0; i < len_align; i += 16) {
> tcg_gen_ld_i64(t0, base, vofs + i);
> tcg_gen_ld_i64(t1, base, vofs + i + 8);
> tcg_gen_concat_i64_i128(t16, t0, t1);
> --
This fixes the test case I have for vector lengths of 64 bytes
and below, but vector lengths above that (eg 128 bytes) still
misbehave in a different way (only every other set of 8 bytes
gets stored). Presumably that's a different bug somewhere else?
thanks
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/arm: Fix SVE STR increment
2023-10-31 10:52 ` Peter Maydell
@ 2023-10-31 14:08 ` Richard Henderson
0 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-10-31 14:08 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, qemu-stable
On 10/31/23 03:52, Peter Maydell wrote:
> On Mon, 30 Oct 2023 at 19:04, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> The previous change missed updating one of the increments.
>>
>> Cc: qemu-stable@nongnu.org
>> Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/tcg/translate-sve.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
>> index 7b39962f20..fc4220114d 100644
>> --- a/target/arm/tcg/translate-sve.c
>> +++ b/target/arm/tcg/translate-sve.c
>> @@ -4294,7 +4294,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
>> t0 = tcg_temp_new_i64();
>> t1 = tcg_temp_new_i64();
>> t16 = tcg_temp_new_i128();
>> - for (i = 0; i < len_align; i += 8) {
>> + for (i = 0; i < len_align; i += 16) {
>> tcg_gen_ld_i64(t0, base, vofs + i);
>> tcg_gen_ld_i64(t1, base, vofs + i + 8);
>> tcg_gen_concat_i64_i128(t16, t0, t1);
>> --
>
> This fixes the test case I have for vector lengths of 64 bytes
> and below, but vector lengths above that (eg 128 bytes) still
> misbehave in a different way (only every other set of 8 bytes
> gets stored). Presumably that's a different bug somewhere else?
Oh yes -- enable-debug yields
qemu-aarch64: ../src/tcg/tcg-op-ldst.c:712: tcg_gen_qemu_st_i128_chk: Assertion `(memop &
MO_SIZE) == MO_128' failed.
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-10-30 19:03 [PATCH] target/arm: Fix SVE STR increment Richard Henderson
2023-10-30 19:29 ` Alex Bennée
2023-10-31 10:52 ` Peter Maydell
2023-10-31 14:08 ` Richard Henderson
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