* [PATCH v2 2/3] hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables.
2023-10-31 13:45 [PATCH v2 0/3] virt: Report UART correctly in ACPI DBG2/SPCR Peter Maydell
2023-10-31 13:45 ` [PATCH v2 1/3] tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2 Peter Maydell
@ 2023-10-31 13:45 ` Peter Maydell
2023-10-31 13:45 ` [PATCH v2 3/3] tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references Peter Maydell
2023-11-02 16:28 ` [PATCH v2 0/3] virt: Report UART correctly in ACPI DBG2/SPCR Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2023-10-31 13:45 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Udo Steinberg
From: Udo Steinberg <udo@hypervisor.org>
Documentation for using the GAS in ACPI tables to report debug UART addresses at
https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table
states the following:
- The Register Bit Width field contains the register stride and must be a
power of 2 that is at least as large as the access size. On 32-bit
platforms this value cannot exceed 32. On 64-bit platforms this value
cannot exceed 64.
- The Access Size field is used to determine whether byte, WORD, DWORD, or
QWORD accesses are to be used. QWORD accesses are only valid on 64-bit
architectures.
Documentation for the ARM PL011 at
https://developer.arm.com/documentation/ddi0183/latest/
states that the registers are:
- spaced 4 bytes apart (see Table 3-2), so register stride must be 32.
- 16 bits in size (see individual registers), so access size must be 2.
The PL011 documentation does not mention whether 8-bit accesses or 32-bit
accesses to the registers are also allowed. Because a standard PL011 (not
the SBSA version) is connected via a 16-bit bus using PWDATA[15:0] and
PRDATA[15:0] (see Figure 2-1), using 16-bit access is the safest choice.
For SBSA-compatible UARTs the DBG2/SPCR table should report a different
subtype (0xd or 0xe) instead of 0x3.
Linux doesn't seem to care about this error in the table, but it does
affect at least the NOVA microhypervisor.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1938
Signed-off-by: Udo Steinberg <udo@hypervisor.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: minor commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt-acpi-build.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9ce136cd88c..91ed7fc94a1 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -482,7 +482,7 @@ build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
build_append_int_noprefix(table_data, 0, 3); /* Reserved */
/* Base Address */
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 2,
vms->memmap[VIRT_UART].base);
/* Interrupt Type */
build_append_int_noprefix(table_data,
@@ -673,7 +673,7 @@ build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, 34, 2);
/* BaseAddressRegister[] */
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 2,
vms->memmap[VIRT_UART].base);
/* AddressSize[] */
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 3/3] tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references
2023-10-31 13:45 [PATCH v2 0/3] virt: Report UART correctly in ACPI DBG2/SPCR Peter Maydell
2023-10-31 13:45 ` [PATCH v2 1/3] tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2 Peter Maydell
2023-10-31 13:45 ` [PATCH v2 2/3] hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables Peter Maydell
@ 2023-10-31 13:45 ` Peter Maydell
2023-11-02 16:28 ` [PATCH v2 0/3] virt: Report UART correctly in ACPI DBG2/SPCR Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2023-10-31 13:45 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Udo Steinberg
Update the virt SPCR and DBG2 golden reference files to have the
fix for the description of the UART.
Diffs from iasl:
@@ -1,57 +1,57 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/SPCR, Tue Oct 31 12:55:58 2023
+ * Disassembly of /tmp/aml-BA1ND2, Tue Oct 31 12:55:58 2023
*
* ACPI Data Table [SPCR]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table]
[004h 0004 4] Table Length : 00000050
[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : CB
+[009h 0009 1] Checksum : B2
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Interface Type : 03
[025h 0037 3] Reserved : 000000
[028h 0040 12] Serial Port Register : [Generic Address Structure]
[028h 0040 1] Space ID : 00 [SystemMemory]
-[029h 0041 1] Bit Width : 08
+[029h 0041 1] Bit Width : 20
[02Ah 0042 1] Bit Offset : 00
-[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
+[02Bh 0043 1] Encoded Access Width : 02 [Word Access:16]
[02Ch 0044 8] Address : 0000000009000000
[034h 0052 1] Interrupt Type : 08
[035h 0053 1] PCAT-compatible IRQ : 00
[036h 0054 4] Interrupt : 00000021
[03Ah 0058 1] Baud Rate : 03
[03Bh 0059 1] Parity : 00
[03Ch 0060 1] Stop Bits : 01
[03Dh 0061 1] Flow Control : 02
[03Eh 0062 1] Terminal Type : 00
[04Ch 0076 1] Reserved : 00
[040h 0064 2] PCI Device ID : FFFF
[042h 0066 2] PCI Vendor ID : FFFF
[044h 0068 1] PCI Bus : 00
[045h 0069 1] PCI Device : 00
[046h 0070 1] PCI Function : 00
[047h 0071 4] PCI Flags : 00000000
[04Bh 0075 1] PCI Segment : 00
[04Ch 0076 4] Reserved : 00000000
Raw Table Data: Length 80 (0x50)
- 0000: 53 50 43 52 50 00 00 00 02 CB 42 4F 43 48 53 20 // SPCRP.....BOCHS
+ 0000: 53 50 43 52 50 00 00 00 02 B2 42 4F 43 48 53 20 // SPCRP.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................
+ 0020: 01 00 00 00 03 00 00 00 00 20 00 02 00 00 00 09 // ......... ......
0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!.........
0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
@@ -1,57 +1,57 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/DBG2, Tue Oct 31 12:55:58 2023
+ * Disassembly of /tmp/aml-V80ND2, Tue Oct 31 12:55:58 2023
*
* ACPI Data Table [DBG2]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "DBG2" [Debug Port table type 2]
[004h 0004 4] Table Length : 00000057
[008h 0008 1] Revision : 00
-[009h 0009 1] Checksum : CF
+[009h 0009 1] Checksum : B6
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Info Offset : 0000002C
[028h 0040 4] Info Count : 00000001
[02Ch 0044 1] Revision : 00
[02Dh 0045 2] Length : 002B
[02Fh 0047 1] Register Count : 01
[030h 0048 2] Namepath Length : 0005
[032h 0050 2] Namepath Offset : 0026
[034h 0052 2] OEM Data Length : 0000 [Optional field not present]
[036h 0054 2] OEM Data Offset : 0000 [Optional field not present]
[038h 0056 2] Port Type : 8000
[03Ah 0058 2] Port Subtype : 0003
[03Ch 0060 2] Reserved : 0000
[03Eh 0062 2] Base Address Offset : 0016
[040h 0064 2] Address Size Offset : 0022
[042h 0066 12] Base Address Register : [Generic Address Structure]
[042h 0066 1] Space ID : 00 [SystemMemory]
-[043h 0067 1] Bit Width : 08
+[043h 0067 1] Bit Width : 20
[044h 0068 1] Bit Offset : 00
-[045h 0069 1] Encoded Access Width : 01 [Byte Access:8]
+[045h 0069 1] Encoded Access Width : 02 [Word Access:16]
[046h 0070 8] Address : 0000000009000000
[04Eh 0078 4] Address Size : 00001000
[052h 0082 5] Namepath : "COM0"
Raw Table Data: Length 87 (0x57)
- 0000: 44 42 47 32 57 00 00 00 00 CF 42 4F 43 48 53 20 // DBG2W.....BOCHS
+ 0000: 44 42 47 32 57 00 00 00 00 B6 42 4F 43 48 53 20 // DBG2W.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 2C 00 00 00 01 00 00 00 00 2B 00 01 // ....,........+..
0030: 05 00 26 00 00 00 00 00 00 80 03 00 00 00 16 00 // ..&.............
- 0040: 22 00 00 08 00 01 00 00 00 09 00 00 00 00 00 10 // "...............
+ 0040: 22 00 00 20 00 02 00 00 00 09 00 00 00 00 00 10 // ".. ............
0050: 00 00 43 4F 4D 30 00 // ..COM0.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
tests/data/acpi/virt/DBG2 | Bin 87 -> 87 bytes
tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes
3 files changed, 2 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 6673e2c4c13..dfb8523c8bf 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/SPCR",
-"tests/data/acpi/virt/DBG2",
diff --git a/tests/data/acpi/virt/DBG2 b/tests/data/acpi/virt/DBG2
index 86e6314f7b0235ef8ed3e0221e09f996c41f5e98..f9005b5b01a41dbd5a39eb34bdfc4291a23f0021 100644
GIT binary patch
delta 37
ncmWF!=W=m!HwtF}f^8GIEJYL;n1D=95T8MSfx+3|*MI>4b3O$3
delta 37
ncmWF!=W=m!HwtF}g7Xu(EJZjN7=cVq5T8MSfx+3|*MI>4bG-!j
diff --git a/tests/data/acpi/virt/SPCR b/tests/data/acpi/virt/SPCR
index 24e0a579e7d73f432a614380e29aa95113344186..e3bca0ada02c966c867ac91b501260808d6978f1 100644
GIT binary patch
delta 23
ecmWFt;0g|K4hmpkU|`xbkxQOgfq`kFjtT%gQv{~~
delta 23
ecmWFt;0g|K4hmpkU|>2ukxQPLgMo3PjtT%g(gddf
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread