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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id v14-20020adfe4ce000000b0031980783d78sm3651009wrm.54.2023.11.01.02.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:17:05 -0700 (PDT) Date: Wed, 1 Nov 2023 10:17:04 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v7 15/16] target/riscv/tcg: validate profiles during finalize Message-ID: <20231101-937cccb8eb2872360d9b6566@orel> References: <20231031203916.197332-1-dbarboza@ventanamicro.com> <20231031203916.197332-16-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231031203916.197332-16-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Oct 31, 2023 at 05:39:15PM -0300, Daniel Henrique Barboza wrote: > Enabling a profile and then disabling some of its mandatory extensions > is a valid use. It can be useful for debugging and testing. But the > common expected use of enabling a profile is to enable all its mandatory > extensions. > > Add an user warning when mandatory extensions from an enabled profile > are disabled in the command line. We're also going to disable the > profile flag in this case since the profile must include all the > mandatory extensions. This flag can be exposed by QMP to indicate the > actual profile state after the CPU is realized. > > After this patch, this will throw warnings: > > -cpu rv64,rva22u64=true,zihintpause=false,zicbom=false,zicboz=false > > qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension zihintpause > qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension zicbom > qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension zicboz > > Note that the following will NOT throw warnings because the profile is > being enabled last, hence all its mandatory extensions will be enabled: > > -cpu rv64,zihintpause=false,zicbom=false,zicboz=false,rva22u64=true > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/tcg/tcg-cpu.c | 70 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 544f6dd01d..23007b19e4 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -147,6 +147,27 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > g_assert_not_reached(); > } > > +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) > +{ > + const RISCVCPUMultiExtConfig *feat; > + const RISCVIsaExtData *edata; > + > + for (edata = isa_edata_arr; edata && edata->name; edata++) { No need to check edata isn't null since we have the end-of-list, just like feat isn't checked below. > + if (edata->ext_enable_offset == ext_offset) { > + return edata->name; > + } > + } > + > + for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { > + if (feat->offset == ext_offset) { > + return feat->name; > + } > + } > + > + g_assert_not_reached(); > +} > + > + extra blank line here > static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, > bool value) > { > @@ -631,6 +652,54 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > riscv_cpu_disable_priv_spec_isa_exts(cpu); > } > > +static void riscv_cpu_validate_profile(RISCVCPU *cpu, > + RISCVCPUProfile *profile) > +{ > + const char *warn_msg = "Profile %s mandates disabled extension %s"; > + bool send_warn = profile->user_set && profile->enabled; > + bool profile_impl = true; > + int i; > + > + for (i = 0; misa_bits[i] != 0; i++) { > + uint32_t bit = misa_bits[i]; > + > + if (!(profile->misa_ext & bit)) { > + continue; > + } > + > + if (!riscv_has_ext(&cpu->env, bit)) { > + profile_impl = false; > + > + if (send_warn) { > + warn_report(warn_msg, profile->name, > + riscv_get_misa_ext_name(bit)); > + } > + } > + } > + > + for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { > + int ext_offset = profile->ext_offsets[i]; > + > + if (!isa_ext_is_enabled(cpu, ext_offset)) { > + profile_impl = false; > + > + if (send_warn) { > + warn_report(warn_msg, profile->name, > + cpu_cfg_ext_get_name(ext_offset)); > + } > + } > + } > + > + profile->enabled = profile_impl; > +} > + > +static void riscv_cpu_validate_profiles(RISCVCPU *cpu) > +{ > + for (int i = 0; riscv_profiles[i] != NULL; i++) { > + riscv_cpu_validate_profile(cpu, riscv_profiles[i]); > + } > +} > + > void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > { > CPURISCVState *env = &cpu->env; > @@ -649,6 +718,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > } > > riscv_cpu_validate_named_features(cpu); > + riscv_cpu_validate_profiles(cpu); > > if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { > /* > -- > 2.41.0 > Other than the nits, Reviewed-by: Andrew Jones