From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v7 02/16] target/riscv/tcg: do not use "!generic" CPU checks
Date: Wed, 1 Nov 2023 10:20:03 +0100 [thread overview]
Message-ID: <20231101-ec7856944e5893c9ce4c536b@orel> (raw)
In-Reply-To: <20231031203916.197332-3-dbarboza@ventanamicro.com>
On Tue, Oct 31, 2023 at 05:39:02PM -0300, Daniel Henrique Barboza wrote:
> Our current logic in get/setters of MISA and multi-letter extensions
> works because we have only 2 CPU types, generic and vendor, and by using
> "!generic" we're implying that we're talking about vendor CPUs. When adding
> a third CPU type this logic will break so let's handle it beforehand.
>
> In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu instead
> of "not generic". The "generic CPU" checks remaining are from
> riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before
> applying default values for the extensions.
>
> This leaves us with:
>
> - vendor CPUs will not allow extension enablement, all other CPUs will;
>
> - generic CPUs will inherit default values for extensions, all others
> won't.
>
> And now we can add a new, third CPU type, that will allow extensions to
> be enabled and will not inherit defaults, without changing the existing
> logic.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-11-01 9:20 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-31 20:39 [PATCH v7 00/16] rv64i CPU, RVA22U64 profile support Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-11-01 9:19 ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 02/16] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-11-01 9:20 ` Andrew Jones [this message]
2023-10-31 20:39 ` [PATCH v7 03/16] target/riscv: add rv64i CPU Daniel Henrique Barboza
2023-11-01 9:02 ` Andrew Jones
2023-11-01 9:27 ` Daniel Henrique Barboza
2023-11-01 9:47 ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 04/16] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 05/16] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-11-01 9:04 ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 06/16] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 07/16] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 08/16] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 09/16] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 10/16] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 11/16] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 12/16] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 13/16] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 14/16] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 15/16] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2023-11-01 9:17 ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 16/16] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2023-11-01 9:19 ` Andrew Jones
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