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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH v2 17/21] target/sparc: Record entire jump condition in DisasContext
Date: Tue, 31 Oct 2023 21:11:28 -0700	[thread overview]
Message-ID: <20231101041132.174501-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231101041132.174501-1-richard.henderson@linaro.org>

Use the original condition instead of consuming cpu_cond,
which will now only be live along exception paths.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 0bbe4cff3b..5c9a3d45fa 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -146,6 +146,12 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS];
 # define env64_field_offsetof(X)  ({ qemu_build_not_reached(); 0; })
 #endif
 
+typedef struct DisasCompare {
+    TCGCond cond;
+    TCGv c1;
+    int c2;
+} DisasCompare;
+
 typedef struct DisasDelayException {
     struct DisasDelayException *next;
     TCGLabel *lab;
@@ -159,7 +165,11 @@ typedef struct DisasContext {
     DisasContextBase base;
     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
-    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
+
+    /* Used when JUMP_PC value is used. */
+    DisasCompare jump;
+    target_ulong jump_pc[2];
+
     int mem_idx;
     bool fpu_enabled;
     bool address_mask_32bit;
@@ -178,12 +188,6 @@ typedef struct DisasContext {
     DisasDelayException *delay_excp_list;
 } DisasContext;
 
-typedef struct {
-    TCGCond cond;
-    TCGv c1;
-    int c2;
-} DisasCompare;
-
 // This function uses non-native bit order
 #define GET_FIELD(X, FROM, TO)                                  \
     ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
@@ -912,9 +916,9 @@ static void gen_generic_branch(DisasContext *dc)
 {
     TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]);
     TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]);
-    TCGv zero = tcg_constant_tl(0);
+    TCGv c2 = tcg_constant_tl(dc->jump.c2);
 
-    tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
+    tcg_gen_movcond_tl(dc->jump.cond, cpu_npc, dc->jump.c1, c2, npc0, npc1);
 }
 
 /* call this function before using the condition register as it may
@@ -2347,7 +2351,7 @@ static bool advance_pc(DisasContext *dc)
         case JUMP_PC:
             /* we can do a static jump */
             l1 = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cond, 0, l1);
+            tcg_gen_brcondi_tl(dc->jump.cond, dc->jump.c1, dc->jump.c2, l1);
 
             /* jump not taken */
             gen_goto_tb(dc, 1, dc->jump_pc[1], dc->jump_pc[1] + 4);
@@ -2434,9 +2438,10 @@ static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
             }
         } else {
             dc->pc = npc;
+            dc->npc = JUMP_PC;
+            dc->jump = *cmp;
             dc->jump_pc[0] = dest;
             dc->jump_pc[1] = npc + 4;
-            dc->npc = JUMP_PC;
 
             /* The condition for cpu_cond is always NE -- normalize. */
             if (cmp->cond == TCG_COND_NE) {
-- 
2.34.1



  parent reply	other threads:[~2023-11-01  4:16 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-01  4:11 [PATCH v2 00/21] target/sparc: Cleanup condition codes etc Richard Henderson
2023-11-01  4:11 ` [PATCH v2 01/21] target/sparc: Introduce cpu_put_psr_icc Richard Henderson
2023-11-01  4:11 ` [PATCH v2 02/21] target/sparc: Split psr and xcc into components Richard Henderson
2023-11-01  4:11 ` [PATCH v2 03/21] target/sparc: Remove CC_OP_LOGIC Richard Henderson
2023-11-01  4:11 ` [PATCH v2 04/21] target/sparc: Remove CC_OP_DIV Richard Henderson
2023-11-01  4:11 ` [PATCH v2 05/21] target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD Richard Henderson
2023-11-01  4:11 ` [PATCH v2 06/21] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB Richard Henderson
2023-11-01  4:11 ` [PATCH v2 07/21] target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV Richard Henderson
2023-11-01  4:11 ` [PATCH v2 08/21] target/sparc: Remove CC_OP leftovers Richard Henderson
2023-11-01  4:11 ` [PATCH v2 09/21] target/sparc: Remove DisasCompare.is_bool Richard Henderson
2023-11-01  4:11 ` [PATCH v2 10/21] target/sparc: Change DisasCompare.c2 to int Richard Henderson
2023-11-01  4:11 ` [PATCH v2 11/21] target/sparc: Always copy conditions into a new temporary Richard Henderson
2023-11-01  4:11 ` [PATCH v2 12/21] target/sparc: Do flush_cond in advance_jump_cond Richard Henderson
2023-11-01  4:11 ` [PATCH v2 13/21] target/sparc: Merge gen_branch2 into advance_pc Richard Henderson
2023-11-01  4:11 ` [PATCH v2 14/21] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond Richard Henderson
2023-11-01  4:11 ` [PATCH v2 15/21] target/sparc: Pass displacement to advance_jump_cond Richard Henderson
2023-11-01  4:11 ` [PATCH v2 16/21] target/sparc: Merge gen_op_next_insn into only caller Richard Henderson
2023-11-01  4:11 ` Richard Henderson [this message]
2023-11-01  4:11 ` [PATCH v2 18/21] target/sparc: Discard cpu_cond at the end of each insn Richard Henderson
2023-11-01  4:11 ` [PATCH v2 19/21] target/sparc: Implement UDIVX and SDIVX inline Richard Henderson
2023-11-01  4:11 ` [PATCH v2 20/21] target/sparc: Implement UDIV inline Richard Henderson
2023-11-01  4:11 ` [PATCH v2 21/21] target/sparc: Check for invalid cond in gen_compare_reg Richard Henderson
2023-11-05 13:22 ` [PATCH v2 00/21] target/sparc: Cleanup condition codes etc Mark Cave-Ayland

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