From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH v2 20/21] target/sparc: Implement UDIV inline
Date: Tue, 31 Oct 2023 21:11:31 -0700 [thread overview]
Message-ID: <20231101041132.174501-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231101041132.174501-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 3 +-
target/sparc/translate.c | 67 +++++++++++++++++++++++++++++++--------
2 files changed, 56 insertions(+), 14 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 52f54b87cc..2d26404cb2 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -184,7 +184,8 @@ MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri
-UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
+UDIV 10 ..... 001110 ..... . ............. @r_r_ri
+UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri_cc1
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 95cc4c71f4..4b7d943bae 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -577,18 +577,6 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
gen_op_multiply(dst, src1, src2, 1);
}
-static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
-{
-#ifdef TARGET_SPARC64
- gen_helper_udiv(dst, tcg_env, src1, src2);
- tcg_gen_ext32u_tl(dst, dst);
-#else
- TCGv_i64 t64 = tcg_temp_new_i64();
- gen_helper_udiv(t64, tcg_env, src1, src2);
- tcg_gen_trunc_i64_tl(dst, t64);
-#endif
-}
-
static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
{
#ifdef TARGET_SPARC64
@@ -3568,7 +3556,7 @@ TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc)
-TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc)
+TRANS(UDIVcc, DIV, do_arith, a, NULL, NULL, gen_op_udivcc)
TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc)
/* TODO: Should have feature bit -- comes in with UltraSparc T2. */
@@ -3591,6 +3579,59 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
}
+static bool trans_UDIV(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv_i64 t1, t2;
+ TCGv dst;
+
+ if (!avail_DIV(dc)) {
+ return false;
+ }
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!a->imm && a->rs2_or_imm & ~0x1f) {
+ return false;
+ }
+
+ if (unlikely(a->rs2_or_imm == 0)) {
+ gen_exception(dc, TT_DIV_ZERO);
+ return true;
+ }
+
+ if (a->imm) {
+ t2 = tcg_constant_i64((uint32_t)a->rs2_or_imm);
+ } else {
+ TCGLabel *lab;
+ TCGv_i32 n2;
+
+ finishing_insn(dc);
+ flush_cond(dc);
+
+ n2 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]);
+
+ lab = delay_exception(dc, TT_DIV_ZERO);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, n2, 0, lab);
+
+ t2 = tcg_temp_new_i64();
+#ifdef TARGET_SPARC64
+ tcg_gen_ext32u_i64(t2, cpu_regs[a->rs2_or_imm]);
+#else
+ tcg_gen_extu_i32_i64(t2, cpu_regs[a->rs2_or_imm]);
+#endif
+ }
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_concat_tl_i64(t1, gen_load_gpr(dc, a->rs1), cpu_y);
+
+ tcg_gen_divu_i64(t1, t1, t2);
+ tcg_gen_umin_i64(t1, t1, tcg_constant_i64(UINT32_MAX));
+
+ dst = gen_dest_gpr(dc, a->rd);
+ tcg_gen_trunc_i64_tl(dst, t1);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a)
{
TCGv dst, src1, src2;
--
2.34.1
next prev parent reply other threads:[~2023-11-01 4:14 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-01 4:11 [PATCH v2 00/21] target/sparc: Cleanup condition codes etc Richard Henderson
2023-11-01 4:11 ` [PATCH v2 01/21] target/sparc: Introduce cpu_put_psr_icc Richard Henderson
2023-11-01 4:11 ` [PATCH v2 02/21] target/sparc: Split psr and xcc into components Richard Henderson
2023-11-01 4:11 ` [PATCH v2 03/21] target/sparc: Remove CC_OP_LOGIC Richard Henderson
2023-11-01 4:11 ` [PATCH v2 04/21] target/sparc: Remove CC_OP_DIV Richard Henderson
2023-11-01 4:11 ` [PATCH v2 05/21] target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD Richard Henderson
2023-11-01 4:11 ` [PATCH v2 06/21] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB Richard Henderson
2023-11-01 4:11 ` [PATCH v2 07/21] target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV Richard Henderson
2023-11-01 4:11 ` [PATCH v2 08/21] target/sparc: Remove CC_OP leftovers Richard Henderson
2023-11-01 4:11 ` [PATCH v2 09/21] target/sparc: Remove DisasCompare.is_bool Richard Henderson
2023-11-01 4:11 ` [PATCH v2 10/21] target/sparc: Change DisasCompare.c2 to int Richard Henderson
2023-11-01 4:11 ` [PATCH v2 11/21] target/sparc: Always copy conditions into a new temporary Richard Henderson
2023-11-01 4:11 ` [PATCH v2 12/21] target/sparc: Do flush_cond in advance_jump_cond Richard Henderson
2023-11-01 4:11 ` [PATCH v2 13/21] target/sparc: Merge gen_branch2 into advance_pc Richard Henderson
2023-11-01 4:11 ` [PATCH v2 14/21] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond Richard Henderson
2023-11-01 4:11 ` [PATCH v2 15/21] target/sparc: Pass displacement to advance_jump_cond Richard Henderson
2023-11-01 4:11 ` [PATCH v2 16/21] target/sparc: Merge gen_op_next_insn into only caller Richard Henderson
2023-11-01 4:11 ` [PATCH v2 17/21] target/sparc: Record entire jump condition in DisasContext Richard Henderson
2023-11-01 4:11 ` [PATCH v2 18/21] target/sparc: Discard cpu_cond at the end of each insn Richard Henderson
2023-11-01 4:11 ` [PATCH v2 19/21] target/sparc: Implement UDIVX and SDIVX inline Richard Henderson
2023-11-01 4:11 ` Richard Henderson [this message]
2023-11-01 4:11 ` [PATCH v2 21/21] target/sparc: Check for invalid cond in gen_compare_reg Richard Henderson
2023-11-05 13:22 ` [PATCH v2 00/21] target/sparc: Cleanup condition codes etc Mark Cave-Ayland
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