From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp()
Date: Thu, 2 Nov 2023 10:24:16 +0100 [thread overview]
Message-ID: <20231102-b74e75db47b353355c6e5d66@orel> (raw)
In-Reply-To: <20231101204204.345470-4-dbarboza@ventanamicro.com>
On Wed, Nov 01, 2023 at 05:41:48PM -0300, Daniel Henrique Barboza wrote:
> The setter() for the boolean attributes that set satp_mode (sv32, sv39,
> sv48, sv57, sv64) considers that the CPU will always do a
> set_satp_mode_max_supported() during cpu_init().
>
> This is not the case for the KVM 'host' CPU, and we'll add another CPU
> that won't set satp_mode_max() during cpu_init(). Users should be able
> to set a max_support in these circunstances.
>
> Allow cpu_riscv_set_satp() to set satp_mode_max_supported if the CPU
> didn't set one prior.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 822970345c..9f6837ecb7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1100,6 +1100,7 @@ static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
> static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
> void *opaque, Error **errp)
> {
> + RISCVCPU *cpu = RISCV_CPU(obj);
> RISCVSATPMap *satp_map = opaque;
> uint8_t satp = satp_mode_from_str(name);
> bool value;
> @@ -1108,6 +1109,16 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
> return;
> }
>
> + /*
> + * Allow users to set satp max supported if the CPU didn't
> + * set any during cpu_init(). First value set to 'true'
> + * in this case is assumed to be the max supported for
> + * the CPU.
Hmm, doesn't that mean if a user does
-cpu rv64,sv39=true,sv48=true
then the max is set to sv39 instead of sv48?
I made a mistake in my last review by stating we shouldn't set the max
supported satp for rv64i to the maximum satp that TCG supports. I forgot
how all of it worked. Setting the _supported_ modes to the maximum that
TCG supports makes sense as long as we don't default to any of them for
rv64i. So, I think we should return the set_satp_mode_max_supported() to
rv64i's definition (passing VM_1_10_SV57 or maybe even VM_1_10_SV64) and
then change set_satp_mode_default_map() to error out for rv64i (or maybe
for all "bare" type cpus).
> + */
> + if (value && cpu->cfg.satp_mode.supported == 0) {
> + set_satp_mode_max_supported(cpu, satp);
> + }
> +
> satp_map->map = deposit32(satp_map->map, satp, 1, value);
> satp_map->init |= 1 << satp;
> }
> --
> 2.41.0
>
Thanks,
drew
next prev parent reply other threads:[~2023-11-02 9:25 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-01 20:41 [PATCH v8 00/19] rv64i CPU, RVA22U64 profile support Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 01/19] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-11-02 2:32 ` Alistair Francis
2023-11-01 20:41 ` [PATCH v8 02/19] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-11-02 2:38 ` Alistair Francis
2023-11-01 20:41 ` [PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp() Daniel Henrique Barboza
2023-11-02 9:24 ` Andrew Jones [this message]
2023-11-02 12:53 ` Daniel Henrique Barboza
2023-11-02 13:11 ` Andrew Jones
2023-11-01 20:41 ` [PATCH v8 04/19] target/riscv/cpu.c: set satp_mode_max MBARE during satp_finalize() Daniel Henrique Barboza
2023-11-02 9:32 ` Andrew Jones
2023-11-01 20:41 ` [PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2023-11-02 9:47 ` Andrew Jones
2023-11-02 13:42 ` Daniel Henrique Barboza
2023-11-02 13:48 ` Andrew Jones
2023-11-01 20:41 ` [PATCH v8 06/19] target/riscv: add rv64i CPU Daniel Henrique Barboza
2023-11-02 9:59 ` Andrew Jones
2023-11-02 14:23 ` Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 07/19] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 08/19] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 09/19] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 10/19] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 11/19] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 12/19] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 13/19] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 14/19] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 15/19] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 16/19] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 17/19] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 18/19] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 19/19] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
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