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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id h11-20020a056000000b00b0031980783d78sm1953618wrx.54.2023.11.02.02.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 02:47:16 -0700 (PDT) Date: Thu, 2 Nov 2023 10:47:15 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions Message-ID: <20231102-bdcd40a9183dbbfe6667a304@orel> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> <20231101204204.345470-6-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231101204204.345470-6-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Nov 01, 2023 at 05:41:50PM -0300, Daniel Henrique Barboza wrote: > We'll add a new bare CPU type that won't have any default priv_ver. This > means that the CPU will default to priv_ver = 0, i.e. 1.10.0. > > At the same we'll allow these CPUs to enable extensions at will, but > then, if the extension has a priv_ver newer than 1.10, we'll end up > disabling it. Users will then need to manually set priv_ver to something > other than 1.10 to enable the extensions they want, which is not ideal. > > Change the setter() of multi letter extensions to allow user enabled > extensions to bump the priv_ver of the CPU. This will make it > conveniente for users to enable extensions for CPUs that doesn't set a > default priv_ver. > > This change does not affect any existing CPU: vendor CPUs does not allow > extensions to be enabled, and generic CPUs are already set to priv_ver > LATEST. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index f54069d06f..b88fce98a4 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -114,6 +114,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > g_assert_not_reached(); > } > > +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, > + uint32_t ext_offset) > +{ > + int ext_priv_ver; > + > + if (env->priv_ver == PRIV_VERSION_LATEST) { > + return; > + } > + > + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); > + > + if (env->priv_ver < ext_priv_ver) { > + env->priv_ver = ext_priv_ver; > + } This will ignore user input. If the user, for example, does -cpu rv64,priv_spec=v1.10.0,zicbom=on then, afaict, priv_spec will be silently bumped to 1.12. I think we should error out in that case instead. And, we should also error out for -cpu rv64,zicbom=on,priv_spec=v1.10.0 which means we should know when priv_spec is either - its default value - has been bumped by an extension - has been explicitly set by the user > +} > + > static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, > bool value) > { > @@ -829,6 +845,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, > return; > } > > + if (value) { > + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); > + } Some misa extensions also have priv spec version dependencies. See riscv_cpu_validate_misa_priv() > + > isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); > } > > -- > 2.41.0 > Thanks, drew