From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH v3 01/88] target/hppa: Include PSW_P in tb flags and mmu index
Date: Wed, 1 Nov 2023 18:28:49 -0700 [thread overview]
Message-ID: <20231102013016.369010-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231102013016.369010-1-richard.henderson@linaro.org>
Use a separate mmu index for PSW_P enabled vs disabled.
This means we can elide the tlb flush in cpu_hppa_put_psw
when PSW_P changes. This turns out to be the majority
of all tlb flushes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 36 ++++++++++++++++++++++++------------
target/hppa/helper.c | 8 --------
target/hppa/mem_helper.c | 6 ++----
target/hppa/translate.c | 5 +++--
4 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 798d0c26d7..48d735929e 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -30,21 +30,33 @@
basis. It's probably easier to fall back to a strong memory model. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-#define MMU_KERNEL_IDX 11
-#define MMU_PL1_IDX 12
-#define MMU_PL2_IDX 13
-#define MMU_USER_IDX 14
-#define MMU_PHYS_IDX 15
+#define MMU_KERNEL_IDX 7
+#define MMU_KERNEL_P_IDX 8
+#define MMU_PL1_IDX 9
+#define MMU_PL1_P_IDX 10
+#define MMU_PL2_IDX 11
+#define MMU_PL2_P_IDX 12
+#define MMU_USER_IDX 13
+#define MMU_USER_P_IDX 14
+#define MMU_PHYS_IDX 15
-#define PRIV_TO_MMU_IDX(priv) (MMU_KERNEL_IDX + (priv))
-#define MMU_IDX_TO_PRIV(mmu_idx) ((mmu_idx) - MMU_KERNEL_IDX)
+#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
+#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
+#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
#define TARGET_INSN_START_EXTRA_WORDS 1
/* No need to flush MMU_PHYS_IDX */
#define HPPA_MMU_FLUSH_MASK \
- (1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX | \
- 1 << MMU_PL2_IDX | 1 << MMU_USER_IDX)
+ (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \
+ 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \
+ 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
+ 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
+
+/* Indicies to flush for access_id changes. */
+#define HPPA_MMU_FLUSH_P_MASK \
+ (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
+ 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)
/* Hardware exceptions, interrupts, faults, and traps. */
#define EXCP_HPMC 1 /* high priority machine check */
@@ -249,7 +261,7 @@ static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
return MMU_USER_IDX;
#else
if (env->psw & (ifetch ? PSW_C : PSW_D)) {
- return PRIV_TO_MMU_IDX(env->iaoq_f & 3);
+ return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
}
return MMU_PHYS_IDX; /* mmu disabled */
#endif
@@ -299,8 +311,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
*cs_base = env->iaoq_b & -4;
flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
#else
- /* ??? E, T, H, L, B, P bits need to be here, when implemented. */
- flags |= env->psw & (PSW_W | PSW_C | PSW_D);
+ /* ??? E, T, H, L, B bits need to be here, when implemented. */
+ flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
*pc = (env->psw & PSW_C
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index a8d3f456ee..cba8160b3d 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -51,7 +51,6 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
{
- target_ureg old_psw = env->psw;
target_ureg cb = 0;
env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
@@ -67,13 +66,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
cb |= ((psw >> 9) & 1) << 8;
cb |= ((psw >> 8) & 1) << 4;
env->psw_cb = cb;
-
- /* If PSW_P changes, it affects how we translate addresses. */
- if ((psw ^ old_psw) & PSW_P) {
-#ifndef CONFIG_USER_ONLY
- tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
-#endif
- }
}
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 350485f619..729032288d 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -144,7 +144,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
}
/* access_id == 0 means public page and no check is performed */
- if ((env->psw & PSW_P) && ent->access_id) {
+ if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) {
/* If bits [31:1] match, and bit 0 is set, suppress write. */
int match = ent->access_id * 2 + 1;
@@ -373,9 +373,7 @@ void HELPER(ptlbe)(CPUHPPAState *env)
void cpu_hppa_change_prot_id(CPUHPPAState *env)
{
- if (env->psw & PSW_P) {
- tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
- }
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_P_MASK);
}
void HELPER(change_prot_id)(CPUHPPAState *env)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 9f3ba9f42f..f6a656325c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4071,8 +4071,9 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
- ctx->mmu_idx = (ctx->tb_flags & PSW_D ?
- PRIV_TO_MMU_IDX(ctx->privilege) : MMU_PHYS_IDX);
+ ctx->mmu_idx = (ctx->tb_flags & PSW_D
+ ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P)
+ : MMU_PHYS_IDX);
/* Recover the IAOQ values from the GVA + PRIV. */
uint64_t cs_base = ctx->base.tb->cs_base;
--
2.34.1
next prev parent reply other threads:[~2023-11-02 1:36 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-02 1:28 [PATCH v3 00/88] target/hppa: Implement hppa64 cpu Richard Henderson
2023-11-02 1:28 ` Richard Henderson [this message]
2023-11-02 1:28 ` [PATCH v3 02/88] target/hppa: Rename hppa_tlb_entry to HPPATLBEntry Richard Henderson
2023-11-02 1:28 ` [PATCH v3 03/88] target/hppa: Use IntervalTreeNode in HPPATLBEntry Richard Henderson
2023-11-02 1:28 ` [PATCH v3 04/88] target/hppa: Always report one page to tlb_set_page Richard Henderson
2023-11-02 1:28 ` [PATCH v3 05/88] target/hppa: Split out hppa_flush_tlb_range Richard Henderson
2023-11-02 1:28 ` [PATCH v3 06/88] target/hppa: Populate an interval tree with valid tlb entries Richard Henderson
2023-11-02 1:28 ` [PATCH v3 07/88] tcg: Improve expansion of deposit of constant Richard Henderson
2023-11-02 1:28 ` [PATCH v3 08/88] tcg: Improve expansion of deposit into a constant Richard Henderson
2023-11-02 1:28 ` [PATCH v3 09/88] target/hppa: Remove get_temp Richard Henderson
2023-11-02 1:28 ` [PATCH v3 10/88] target/hppa: Remove get_temp_tl Richard Henderson
2023-11-02 1:28 ` [PATCH v3 11/88] target/hppa: Remove load_const Richard Henderson
2023-11-02 1:29 ` [PATCH v3 12/88] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-11-02 1:29 ` [PATCH v3 13/88] target/hppa: Fix load in do_load_32 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 14/88] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-11-02 1:29 ` [PATCH v3 15/88] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 16/88] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 17/88] target/hppa: Fix bb_sar " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 18/88] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 19/88] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-11-02 1:29 ` [PATCH v3 20/88] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-11-02 1:29 ` [PATCH v3 21/88] target/hppa: Implement cpu_list Richard Henderson
2023-11-02 1:29 ` [PATCH v3 22/88] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-11-02 1:29 ` [PATCH v3 23/88] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 24/88] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 25/88] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 26/88] target/hppa: Fix hppa64 addressing Richard Henderson
2023-11-02 1:29 ` [PATCH v3 27/88] target/hppa: Pass DisasContext to copy_iaoq_entry Richard Henderson
2023-11-02 1:29 ` [PATCH v3 28/88] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] Richard Henderson
2023-11-02 1:29 ` [PATCH v3 29/88] target/hppa: Use copy_iaoq_entry for link in do_ibranch Richard Henderson
2023-11-02 1:29 ` [PATCH v3 30/88] target/hppa: Mask inputs in copy_iaoq_entry Richard Henderson
2023-11-02 1:29 ` [PATCH v3 31/88] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-11-02 1:29 ` [PATCH v3 32/88] target/hppa: Pass d to do_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 33/88] target/hppa: Pass d to do_sub_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 34/88] target/hppa: Pass d to do_log_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 35/88] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 36/88] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 37/88] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 38/88] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 39/88] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 40/88] target/hppa: Decode d for logical instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 41/88] target/hppa: Decode d for unit instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 42/88] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 43/88] target/hppa: Decode d for add instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 44/88] target/hppa: Decode d for sub instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 45/88] target/hppa: Decode d for bb instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 46/88] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 47/88] target/hppa: Decode CMPIB double-word Richard Henderson
2023-11-02 1:29 ` [PATCH v3 48/88] target/hppa: Decode ADDB double-word Richard Henderson
2023-11-02 1:29 ` [PATCH v3 49/88] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-11-02 1:29 ` [PATCH v3 50/88] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-11-02 1:29 ` [PATCH v3 51/88] target/hppa: Implement EXTRD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 52/88] target/hppa: Implement SHRPD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 53/88] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-11-02 1:29 ` [PATCH v3 54/88] target/hppa: Implement STDBY Richard Henderson
2023-11-02 1:29 ` [PATCH v3 55/88] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-11-02 1:29 ` [PATCH v3 56/88] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-11-02 1:29 ` [PATCH v3 57/88] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-11-02 1:29 ` [PATCH v3 58/88] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-11-02 1:29 ` [PATCH v3 59/88] target/hppa: Remove remaining " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 60/88] target/hppa: Adjust vmstate_env for pa2.0 tlb Richard Henderson
2023-11-02 1:29 ` [PATCH v3 61/88] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-11-02 1:29 ` [PATCH v3 62/88] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 63/88] target/hppa: Implement HADD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 64/88] target/hppa: Implement HSUB Richard Henderson
2023-11-02 1:29 ` [PATCH v3 65/88] target/hppa: Implement HAVG Richard Henderson
2023-11-02 1:29 ` [PATCH v3 66/88] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-11-02 1:29 ` [PATCH v3 67/88] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 68/88] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-11-02 1:29 ` [PATCH v3 69/88] target/hppa: Implement PERMH Richard Henderson
2023-11-02 1:29 ` [PATCH v3 70/88] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-11-02 1:29 ` [PATCH v3 71/88] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-11-02 1:30 ` [PATCH v3 72/88] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-11-02 1:30 ` [PATCH v3 73/88] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-11-02 1:30 ` [PATCH v3 74/88] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-11-02 1:30 ` [PATCH v3 75/88] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
2023-11-02 1:30 ` [PATCH v3 76/88] target/hppa: Implement pa2.0 data prefetch instructions Richard Henderson
2023-11-02 1:30 ` [PATCH v3 77/88] target/hppa: Add pa2.0 cpu local tlb flushes Richard Henderson
2023-11-02 1:30 ` [PATCH v3 78/88] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system Richard Henderson
2023-11-02 1:30 ` [PATCH v3 79/88] target/hppa: Clear upper bits in mtctl for pa1.x Richard Henderson
2023-11-02 1:30 ` [PATCH v3 80/88] target/hppa: Add unwind_breg to CPUHPPAState Richard Henderson
2023-11-02 1:30 ` [PATCH v3 81/88] target/hppa: Create raise_exception_with_ior Richard Henderson
2023-11-02 1:30 ` [PATCH v3 82/88] target/hppa: Update IIAOQ, IIASQ for pa2.0 Richard Henderson
2023-11-02 1:30 ` [PATCH v3 83/88] target/hppa: Improve interrupt logging Richard Henderson
2023-11-02 1:30 ` [PATCH v3 84/88] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region Richard Henderson
2023-11-02 1:30 ` [PATCH v3 85/88] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory Richard Henderson
2023-11-02 1:30 ` [PATCH v3 86/88] hw/hppa: Turn on 64-bit CPU for C3700 machine Richard Henderson
2023-11-02 1:30 ` [PATCH v3 87/88] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only Richard Henderson
2023-11-02 1:30 ` [PATCH v3 88/88] hw/hppa: Map PDC ROM and I/O memory area into lower memory Richard Henderson
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