From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH v3 32/88] target/hppa: Pass d to do_cond
Date: Wed, 1 Nov 2023 18:29:20 -0700 [thread overview]
Message-ID: <20231102013016.369010-33-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231102013016.369010-1-richard.henderson@linaro.org>
Hoist the resolution of d up one level above do_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 82 +++++++++++++++++++++++++++--------------
1 file changed, 54 insertions(+), 28 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1694b988ae..7b0e48c42b 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -827,7 +827,7 @@ static bool cond_need_cb(int c)
/* Need extensions from TCGv_i32 to TCGv_reg. */
static bool cond_need_ext(DisasContext *ctx, bool d)
{
- return TARGET_REGISTER_BITS == 64 && !d;
+ return TARGET_REGISTER_BITS == 64 && !(ctx->is_pa20 && d);
}
/*
@@ -835,8 +835,8 @@ static bool cond_need_ext(DisasContext *ctx, bool d)
* the Parisc 1.1 Architecture Reference Manual for details.
*/
-static DisasCond do_cond(unsigned cf, TCGv_reg res,
- TCGv_reg cb_msb, TCGv_reg sv)
+static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
+ TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv)
{
DisasCond cond;
TCGv_reg tmp;
@@ -846,11 +846,19 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res,
cond = cond_make_f();
break;
case 1: /* = / <> (Z / !Z) */
+ if (cond_need_ext(ctx, d)) {
+ tmp = tcg_temp_new();
+ tcg_gen_ext32u_reg(tmp, res);
+ res = tmp;
+ }
cond = cond_make_0(TCG_COND_EQ, res);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new();
tcg_gen_xor_reg(tmp, res, sv);
+ if (cond_need_ext(ctx, d)) {
+ tcg_gen_ext32s_reg(tmp, tmp);
+ }
cond = cond_make_0_tmp(TCG_COND_LT, tmp);
break;
case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
@@ -865,20 +873,35 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res,
*/
tmp = tcg_temp_new();
tcg_gen_eqv_reg(tmp, res, sv);
- tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
- tcg_gen_and_reg(tmp, tmp, res);
+ if (cond_need_ext(ctx, d)) {
+ tcg_gen_sextract_reg(tmp, tmp, 31, 1);
+ tcg_gen_and_reg(tmp, tmp, res);
+ tcg_gen_ext32u_reg(tmp, tmp);
+ } else {
+ tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
+ tcg_gen_and_reg(tmp, tmp, res);
+ }
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 4: /* NUV / UV (!C / C) */
+ /* Only bit 0 of cb_msb is ever set. */
cond = cond_make_0(TCG_COND_EQ, cb_msb);
break;
case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
tmp = tcg_temp_new();
tcg_gen_neg_reg(tmp, cb_msb);
tcg_gen_and_reg(tmp, tmp, res);
+ if (cond_need_ext(ctx, d)) {
+ tcg_gen_ext32u_reg(tmp, tmp);
+ }
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 6: /* SV / NSV (V / !V) */
+ if (cond_need_ext(ctx, d)) {
+ tmp = tcg_temp_new();
+ tcg_gen_ext32s_reg(tmp, sv);
+ sv = tmp;
+ }
cond = cond_make_0(TCG_COND_LT, sv);
break;
case 7: /* OD / EV */
@@ -900,10 +923,11 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res,
can use the inputs directly. This can allow other computation to be
deleted as unused. */
-static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
+static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2, TCGv_reg sv)
{
DisasCond cond;
+ bool d = false;
switch (cf >> 1) {
case 1: /* = / <> */
@@ -922,7 +946,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
cond = cond_make(TCG_COND_LEU, in1, in2);
break;
default:
- return do_cond(cf, res, NULL, sv);
+ return do_cond(ctx, cf, d, res, NULL, sv);
}
if (cf & 1) {
cond.c = tcg_invert_cond(cond.c);
@@ -940,8 +964,10 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
* how cases c={2,3} are treated.
*/
-static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
+static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res)
{
+ bool d = false;
+
switch (cf) {
case 0: /* never */
case 9: /* undef, C */
@@ -970,7 +996,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
case 14: /* OD */
case 15: /* EV */
- return do_cond(cf, res, NULL, NULL);
+ return do_cond(ctx, cf, d, res, NULL, NULL);
default:
g_assert_not_reached();
@@ -979,7 +1005,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
/* Similar, but for shift/extract/deposit conditions. */
-static DisasCond do_sed_cond(unsigned orig, TCGv_reg res)
+static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
{
unsigned c, f;
@@ -992,7 +1018,7 @@ static DisasCond do_sed_cond(unsigned orig, TCGv_reg res)
}
f = (orig & 4) / 4;
- return do_log_cond(c * 2 + f, res);
+ return do_log_cond(ctx, c * 2 + f, res);
}
/* Similar, but for unit conditions. */
@@ -1164,7 +1190,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Emit any conditional trap before any writeback. */
- cond = do_cond(cf, dest, cb_cond, sv);
+ cond = do_cond(ctx, cf, d, dest, cb_cond, sv);
if (is_tc) {
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
@@ -1254,9 +1280,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Compute the condition. We cannot use the special case for borrow. */
if (!is_b) {
- cond = do_sub_cond(cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
} else {
- cond = do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv);
+ cond = do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), sv);
}
/* Emit any conditional trap before any writeback. */
@@ -1319,7 +1345,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Form the condition for the compare. */
- cond = do_sub_cond(cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
/* Clear. */
tcg_gen_movi_reg(dest, 0);
@@ -1343,7 +1369,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (cf) {
- ctx->null_cond = do_log_cond(cf, dest);
+ ctx->null_cond = do_log_cond(ctx, cf, dest);
}
}
@@ -2817,7 +2843,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
/* ??? The lshift is supposed to contribute to overflow. */
sv = do_add_sv(ctx, dest, add1, add2);
}
- ctx->null_cond = do_cond(a->cf, dest, cout, sv);
+ ctx->null_cond = do_cond(ctx, a->cf, false, dest, cout, sv);
}
return nullify_end(ctx);
@@ -3034,7 +3060,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_sub_sv(ctx, dest, in1, in2);
}
- cond = do_sub_cond(c * 2 + f, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv);
return do_cbranch(ctx, disp, n, &cond);
}
@@ -3078,7 +3104,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_add_sv(ctx, dest, in1, in2);
}
- cond = do_cond(c * 2 + f, dest, cb_cond, sv);
+ cond = do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv);
save_gpr(ctx, r, dest);
return do_cbranch(ctx, disp, n, &cond);
}
@@ -3149,7 +3175,7 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a)
tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
}
- cond = do_sed_cond(a->c, dest);
+ cond = do_sed_cond(ctx, a->c, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3163,7 +3189,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
dest = dest_gpr(ctx, a->r);
tcg_gen_movi_reg(dest, a->i);
- cond = do_sed_cond(a->c, dest);
+ cond = do_sed_cond(ctx, a->c, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3201,7 +3227,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3237,7 +3263,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3271,7 +3297,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3298,7 +3324,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3335,7 +3361,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3365,7 +3391,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3402,7 +3428,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
- ctx->null_cond = do_sed_cond(c, dest);
+ ctx->null_cond = do_sed_cond(ctx, c, dest);
}
return nullify_end(ctx);
}
--
2.34.1
next prev parent reply other threads:[~2023-11-02 1:32 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-02 1:28 [PATCH v3 00/88] target/hppa: Implement hppa64 cpu Richard Henderson
2023-11-02 1:28 ` [PATCH v3 01/88] target/hppa: Include PSW_P in tb flags and mmu index Richard Henderson
2023-11-02 1:28 ` [PATCH v3 02/88] target/hppa: Rename hppa_tlb_entry to HPPATLBEntry Richard Henderson
2023-11-02 1:28 ` [PATCH v3 03/88] target/hppa: Use IntervalTreeNode in HPPATLBEntry Richard Henderson
2023-11-02 1:28 ` [PATCH v3 04/88] target/hppa: Always report one page to tlb_set_page Richard Henderson
2023-11-02 1:28 ` [PATCH v3 05/88] target/hppa: Split out hppa_flush_tlb_range Richard Henderson
2023-11-02 1:28 ` [PATCH v3 06/88] target/hppa: Populate an interval tree with valid tlb entries Richard Henderson
2023-11-02 1:28 ` [PATCH v3 07/88] tcg: Improve expansion of deposit of constant Richard Henderson
2023-11-02 1:28 ` [PATCH v3 08/88] tcg: Improve expansion of deposit into a constant Richard Henderson
2023-11-02 1:28 ` [PATCH v3 09/88] target/hppa: Remove get_temp Richard Henderson
2023-11-02 1:28 ` [PATCH v3 10/88] target/hppa: Remove get_temp_tl Richard Henderson
2023-11-02 1:28 ` [PATCH v3 11/88] target/hppa: Remove load_const Richard Henderson
2023-11-02 1:29 ` [PATCH v3 12/88] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-11-02 1:29 ` [PATCH v3 13/88] target/hppa: Fix load in do_load_32 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 14/88] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-11-02 1:29 ` [PATCH v3 15/88] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 16/88] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 17/88] target/hppa: Fix bb_sar " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 18/88] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 19/88] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-11-02 1:29 ` [PATCH v3 20/88] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-11-02 1:29 ` [PATCH v3 21/88] target/hppa: Implement cpu_list Richard Henderson
2023-11-02 1:29 ` [PATCH v3 22/88] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-11-02 1:29 ` [PATCH v3 23/88] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 24/88] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 25/88] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 26/88] target/hppa: Fix hppa64 addressing Richard Henderson
2023-11-02 1:29 ` [PATCH v3 27/88] target/hppa: Pass DisasContext to copy_iaoq_entry Richard Henderson
2023-11-02 1:29 ` [PATCH v3 28/88] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] Richard Henderson
2023-11-02 1:29 ` [PATCH v3 29/88] target/hppa: Use copy_iaoq_entry for link in do_ibranch Richard Henderson
2023-11-02 1:29 ` [PATCH v3 30/88] target/hppa: Mask inputs in copy_iaoq_entry Richard Henderson
2023-11-02 1:29 ` [PATCH v3 31/88] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-11-02 1:29 ` Richard Henderson [this message]
2023-11-02 1:29 ` [PATCH v3 33/88] target/hppa: Pass d to do_sub_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 34/88] target/hppa: Pass d to do_log_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 35/88] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 36/88] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-11-02 1:29 ` [PATCH v3 37/88] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 38/88] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 39/88] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 40/88] target/hppa: Decode d for logical instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 41/88] target/hppa: Decode d for unit instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 42/88] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 43/88] target/hppa: Decode d for add instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 44/88] target/hppa: Decode d for sub instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 45/88] target/hppa: Decode d for bb instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 46/88] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-11-02 1:29 ` [PATCH v3 47/88] target/hppa: Decode CMPIB double-word Richard Henderson
2023-11-02 1:29 ` [PATCH v3 48/88] target/hppa: Decode ADDB double-word Richard Henderson
2023-11-02 1:29 ` [PATCH v3 49/88] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-11-02 1:29 ` [PATCH v3 50/88] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-11-02 1:29 ` [PATCH v3 51/88] target/hppa: Implement EXTRD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 52/88] target/hppa: Implement SHRPD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 53/88] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-11-02 1:29 ` [PATCH v3 54/88] target/hppa: Implement STDBY Richard Henderson
2023-11-02 1:29 ` [PATCH v3 55/88] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-11-02 1:29 ` [PATCH v3 56/88] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-11-02 1:29 ` [PATCH v3 57/88] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-11-02 1:29 ` [PATCH v3 58/88] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-11-02 1:29 ` [PATCH v3 59/88] target/hppa: Remove remaining " Richard Henderson
2023-11-02 1:29 ` [PATCH v3 60/88] target/hppa: Adjust vmstate_env for pa2.0 tlb Richard Henderson
2023-11-02 1:29 ` [PATCH v3 61/88] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-11-02 1:29 ` [PATCH v3 62/88] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-11-02 1:29 ` [PATCH v3 63/88] target/hppa: Implement HADD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 64/88] target/hppa: Implement HSUB Richard Henderson
2023-11-02 1:29 ` [PATCH v3 65/88] target/hppa: Implement HAVG Richard Henderson
2023-11-02 1:29 ` [PATCH v3 66/88] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-11-02 1:29 ` [PATCH v3 67/88] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-11-02 1:29 ` [PATCH v3 68/88] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-11-02 1:29 ` [PATCH v3 69/88] target/hppa: Implement PERMH Richard Henderson
2023-11-02 1:29 ` [PATCH v3 70/88] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-11-02 1:29 ` [PATCH v3 71/88] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-11-02 1:30 ` [PATCH v3 72/88] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-11-02 1:30 ` [PATCH v3 73/88] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-11-02 1:30 ` [PATCH v3 74/88] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-11-02 1:30 ` [PATCH v3 75/88] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
2023-11-02 1:30 ` [PATCH v3 76/88] target/hppa: Implement pa2.0 data prefetch instructions Richard Henderson
2023-11-02 1:30 ` [PATCH v3 77/88] target/hppa: Add pa2.0 cpu local tlb flushes Richard Henderson
2023-11-02 1:30 ` [PATCH v3 78/88] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system Richard Henderson
2023-11-02 1:30 ` [PATCH v3 79/88] target/hppa: Clear upper bits in mtctl for pa1.x Richard Henderson
2023-11-02 1:30 ` [PATCH v3 80/88] target/hppa: Add unwind_breg to CPUHPPAState Richard Henderson
2023-11-02 1:30 ` [PATCH v3 81/88] target/hppa: Create raise_exception_with_ior Richard Henderson
2023-11-02 1:30 ` [PATCH v3 82/88] target/hppa: Update IIAOQ, IIASQ for pa2.0 Richard Henderson
2023-11-02 1:30 ` [PATCH v3 83/88] target/hppa: Improve interrupt logging Richard Henderson
2023-11-02 1:30 ` [PATCH v3 84/88] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region Richard Henderson
2023-11-02 1:30 ` [PATCH v3 85/88] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory Richard Henderson
2023-11-02 1:30 ` [PATCH v3 86/88] hw/hppa: Turn on 64-bit CPU for C3700 machine Richard Henderson
2023-11-02 1:30 ` [PATCH v3 87/88] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only Richard Henderson
2023-11-02 1:30 ` [PATCH v3 88/88] hw/hppa: Map PDC ROM and I/O memory area into lower memory Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231102013016.369010-33-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=deller@gmx.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).