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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 00/21] target/sparc: Cleanup condition codes Date: Sun, 5 Nov 2023 12:12:01 -0800 Message-Id: <20231105201222.202395-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following changes since commit d762bf97931b58839316b68a570eecc6143c9e3e: Merge tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-11-03 10:04:12 +0800) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-sp-20231105 for you to fetch changes up to 2c4f56c9aa7e1e8a34428c4efe17788be11fb73f: target/sparc: Check for invalid cond in gen_compare_reg (2023-11-05 12:07:21 -0800) ---------------------------------------------------------------- target/sparc: Explicitly compute condition codes ---------------------------------------------------------------- Richard Henderson (21): target/sparc: Introduce cpu_put_psr_icc target/sparc: Split psr and xcc into components target/sparc: Remove CC_OP_LOGIC target/sparc: Remove CC_OP_DIV target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV target/sparc: Remove CC_OP leftovers target/sparc: Remove DisasCompare.is_bool target/sparc: Change DisasCompare.c2 to int target/sparc: Always copy conditions into a new temporary target/sparc: Do flush_cond in advance_jump_cond target/sparc: Merge gen_branch2 into advance_pc target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond target/sparc: Pass displacement to advance_jump_cond target/sparc: Merge gen_op_next_insn into only caller target/sparc: Record entire jump condition in DisasContext target/sparc: Discard cpu_cond at the end of each insn target/sparc: Implement UDIVX and SDIVX inline target/sparc: Implement UDIV inline target/sparc: Check for invalid cond in gen_compare_reg linux-user/sparc/target_cpu.h | 17 +- target/sparc/cpu.h | 58 +- target/sparc/helper.h | 12 +- target/sparc/insns.decode | 7 +- linux-user/sparc/cpu_loop.c | 11 +- linux-user/sparc/signal.c | 2 +- target/sparc/cc_helper.c | 471 --------------- target/sparc/cpu.c | 1 - target/sparc/helper.c | 171 +++--- target/sparc/int32_helper.c | 5 - target/sparc/int64_helper.c | 5 - target/sparc/machine.c | 45 +- target/sparc/translate.c | 1333 ++++++++++++++++++----------------------- target/sparc/win_helper.c | 56 +- target/sparc/meson.build | 1 - 15 files changed, 789 insertions(+), 1406 deletions(-) delete mode 100644 target/sparc/cc_helper.c