From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org,
qemu-block@nongnu.org, qemu-riscv@nongnu.org,
qemu-ppc@nongnu.org, qemu-arm@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Roman Bolshakov" <roman@roolebo.dev>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Cameron Esfahani" <dirty@apple.com>,
"Roman Bolshakov" <rbolshakov@ddn.com>
Subject: [PULL 24/60] target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]()
Date: Mon, 6 Nov 2023 12:02:56 +0100 [thread overview]
Message-ID: <20231106110336.358-25-philmd@linaro.org> (raw)
In-Reply-To: <20231106110336.358-1-philmd@linaro.org>
When CPUArchState* is available (here CPUX86State*), we can
use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*).
The QOM cast X86_CPU() macro will be slower when building with
--enable-qom-cast-debug.
Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr
instead of a CPUState* to avoid an extra cast.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Roman Bolshakov <roman@roolebo.dev>
Tested-by: Roman Bolshakov <roman@roolebo.dev>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231009110239.66778-7-philmd@linaro.org>
---
target/i386/hvf/x86_emu.h | 4 ++--
target/i386/hvf/hvf.c | 4 ++--
target/i386/hvf/x86_emu.c | 21 ++++++++++-----------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h
index 640da90b30..4b846ba80e 100644
--- a/target/i386/hvf/x86_emu.h
+++ b/target/i386/hvf/x86_emu.h
@@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
-void simulate_rdmsr(struct CPUState *cpu);
-void simulate_wrmsr(struct CPUState *cpu);
+void simulate_rdmsr(CPUX86State *env);
+void simulate_wrmsr(CPUX86State *env);
target_ulong read_reg(CPUX86State *env, int reg, int size);
void write_reg(CPUX86State *env, int reg, target_ulong val, int size);
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index cb2cd0b02f..20b9ca3ef5 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu)
{
load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
- simulate_rdmsr(cpu);
+ simulate_rdmsr(env);
} else {
- simulate_wrmsr(cpu);
+ simulate_wrmsr(env);
}
env->eip += ins_len;
store_regs(cpu);
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index af1f205ecf..b1f8a685d1 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -663,11 +663,10 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
-void simulate_rdmsr(struct CPUState *cpu)
+void simulate_rdmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
- CPUState *cs = env_cpu(env);
+ X86CPU *x86_cpu = env_archcpu(env);
+ CPUState *cpu = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
@@ -746,8 +745,8 @@ void simulate_rdmsr(struct CPUState *cpu)
val = env->mtrr_deftype;
break;
case MSR_CORE_THREAD_COUNT:
- val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
- val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
+ val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */
+ val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */
break;
default:
/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
@@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu)
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
- simulate_rdmsr(env_cpu(env));
+ simulate_rdmsr(env);
env->eip += decode->len;
}
-void simulate_wrmsr(struct CPUState *cpu)
+void simulate_wrmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *x86_cpu = env_archcpu(env);
+ CPUState *cpu = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@@ -856,7 +855,7 @@ void simulate_wrmsr(struct CPUState *cpu)
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
- simulate_wrmsr(env_cpu(env));
+ simulate_wrmsr(env);
env->eip += decode->len;
}
--
2.41.0
next prev parent reply other threads:[~2023-11-06 11:22 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-06 11:02 [PULL 00/60] Misc HW/UI patches for 2023-11-06 Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 01/60] vl: Free machine list Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 02/60] vl: constify default_list Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 03/60] tests/vm/ubuntu.aarch64: Correct comment about TCG specific delay Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 04/60] tests/unit/test-seccomp: Remove mentions of softmmu in test names Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 05/60] accel/tcg: Declare tcg_flush_jmp_cache() in 'exec/tb-flush.h' Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 06/60] accel: Introduce cpu_exec_reset_hold() Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 07/60] accel/tcg: Factor tcg_cpu_reset_hold() out Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 08/60] target: Unify QOM style Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 09/60] target: Mention 'cpu-qom.h' is target agnostic Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 10/60] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h' Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 11/60] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 12/60] target/riscv: " Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 13/60] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 14/60] target/hexagon: Declare QOM definitions " Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 15/60] target/loongarch: " Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 16/60] target/nios2: " Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 17/60] target/openrisc: " Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 18/60] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h' Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 19/60] target/ppc: Use env_archcpu() in helper_book3s_msgsndp() Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 20/60] target/riscv: Use env_archcpu() in [check_]nanbox() Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 21/60] target/s390x: Use env_archcpu() in handle_diag_308() Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 22/60] target/xtensa: Use env_archcpu() in update_c[compare|count]() Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 23/60] target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]() Philippe Mathieu-Daudé
2023-11-06 11:02 ` Philippe Mathieu-Daudé [this message]
2023-11-06 11:02 ` [PULL 25/60] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 26/60] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Philippe Mathieu-Daudé
2023-11-06 11:02 ` [PULL 27/60] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 28/60] target/i386/kvm: Correct comment in kvm_cpu_realize() Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 29/60] target/i386/monitor: synchronize cpu state for lapic info Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 30/60] target/mips: Fix MSA BZ/BNZ opcodes displacement Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 31/60] target/mips: Fix TX79 LQ/SQ opcodes Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 32/60] sysemu/kvm: Restrict kvmppc_get_radix_page_info() to ppc targets Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 33/60] hw/ppc/e500: Restrict ppce500_init_mpic_kvm() to KVM Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 34/60] target/ppc: Restrict KVM objects to system emulation Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 35/60] target/ppc: Prohibit target specific KVM prototypes on user emulation Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 36/60] target/nios2: Create IRQs *after* accelerator vCPU is realized Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 37/60] target/alpha: Tidy up alpha_cpu_class_by_name() Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 38/60] hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 39/60] exec/cpu: Have cpu_exec_realize() return a boolean Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 40/60] hw/cpu: Clean up global variable shadowing Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 41/60] hw/loader: Clean up global variable shadowing in rom_add_file() Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 42/60] hw/isa/i82378: Propagate error if PC_SPEAKER device creation failed Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 43/60] hw/i386: Fix comment style in topology.h Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 44/60] tests/unit: Rename test-x86-cpuid.c to test-x86-topo.c Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 45/60] system/cpus: Fix CPUState.nr_cores' calculation Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 46/60] hw/cpu: Update the comments of nr_cores and nr_dies Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 47/60] hw/ide: reset: cancel async DMA operation before resetting state Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 48/60] tests/qtest: ahci-test: add test exposing reset issue with pending callback Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 49/60] hw/i2c: pmbus add support for block receive Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 50/60] hw/i2c: pmbus: add vout mode bitfields Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 51/60] hw/i2c: pmbus: add fan support Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 52/60] hw/i2c: pmbus: add VCAP register Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 53/60] hw/sensor: add ADM1266 device model Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 54/60] tests/qtest: add tests for ADM1266 Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 55/60] hw/i2c: pmbus: immediately clear faults on request Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 56/60] hw/i2c: pmbus: reset page register for out of range reads Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 57/60] MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 58/60] MAINTAINERS: Add the CAN documentation file to the CAN section Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 59/60] MAINTAINERS: update libvirt devel mailing list address Philippe Mathieu-Daudé
2023-11-06 11:03 ` [PULL 60/60] ui/sdl2: use correct key names in win title on mac Philippe Mathieu-Daudé
2023-11-07 1:39 ` [PULL 00/60] Misc HW/UI patches for 2023-11-06 Stefan Hajnoczi
2023-11-07 8:51 ` Philippe Mathieu-Daudé
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