From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 09/35] tcg: Mark tcg_gen_op* as noinline
Date: Mon, 6 Nov 2023 18:48:16 -0800 [thread overview]
Message-ID: <20231107024842.7650-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231107024842.7650-1-richard.henderson@linaro.org>
Encourage the compiler to tail-call rather than inline
across the dozens of opcode expanders.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-2-richard.henderson@linaro.org>
---
tcg/tcg-op.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 828eb9ee46..9aed19e957 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -31,20 +31,26 @@
#include "tcg-internal.h"
-void tcg_gen_op1(TCGOpcode opc, TCGArg a1)
+/*
+ * Encourage the compiler to tail-call to a function, rather than inlining.
+ * Minimizes code size across 99 bottles of beer on the wall.
+ */
+#define NI __attribute__((noinline))
+
+void NI tcg_gen_op1(TCGOpcode opc, TCGArg a1)
{
TCGOp *op = tcg_emit_op(opc, 1);
op->args[0] = a1;
}
-void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
+void NI tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
{
TCGOp *op = tcg_emit_op(opc, 2);
op->args[0] = a1;
op->args[1] = a2;
}
-void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
+void NI tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
{
TCGOp *op = tcg_emit_op(opc, 3);
op->args[0] = a1;
@@ -52,7 +58,7 @@ void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
op->args[2] = a3;
}
-void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
+void NI tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
{
TCGOp *op = tcg_emit_op(opc, 4);
op->args[0] = a1;
@@ -61,8 +67,8 @@ void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
op->args[3] = a4;
}
-void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
- TCGArg a4, TCGArg a5)
+void NI tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
+ TCGArg a4, TCGArg a5)
{
TCGOp *op = tcg_emit_op(opc, 5);
op->args[0] = a1;
@@ -72,8 +78,8 @@ void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
op->args[4] = a5;
}
-void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
- TCGArg a4, TCGArg a5, TCGArg a6)
+void NI tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
+ TCGArg a4, TCGArg a5, TCGArg a6)
{
TCGOp *op = tcg_emit_op(opc, 6);
op->args[0] = a1;
--
2.34.1
next prev parent reply other threads:[~2023-11-07 2:55 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-07 2:48 [PATCH 00/35] tcg patch queue Richard Henderson
2023-11-07 2:48 ` [PATCH 01/35] accel/tcg: Move HMP info jit and info opcount code Richard Henderson
2023-11-07 2:48 ` [PATCH 02/35] tcg: Add C_N2_I1 Richard Henderson
2023-11-07 2:48 ` [PATCH 03/35] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 Richard Henderson
2023-11-07 2:48 ` [PATCH 04/35] util: Add cpuinfo for loongarch64 Richard Henderson
2023-11-07 2:48 ` [PATCH 05/35] tcg/loongarch64: Use cpuinfo.h Richard Henderson
2023-11-07 2:48 ` [PATCH 06/35] host/include/loongarch64: Add atomic16 load and store Richard Henderson
2023-11-07 2:48 ` [PATCH 07/35] accel/tcg: Remove redundant case in store_atom_16 Richard Henderson
2023-11-07 2:48 ` [PATCH 08/35] accel/tcg: Fix condition for store_atom_insert_al16 Richard Henderson
2023-11-07 2:48 ` Richard Henderson [this message]
2023-11-07 2:48 ` [PATCH 10/35] tcg: Move tcg_gen_op* out of line Richard Henderson
2023-11-07 2:48 ` [PATCH 11/35] tcg: Move generic expanders " Richard Henderson
2023-11-07 2:48 ` [PATCH 12/35] tcg: Move 32-bit " Richard Henderson
2023-11-07 2:48 ` [PATCH 13/35] tcg: Move 64-bit " Richard Henderson
2023-11-07 2:48 ` [PATCH 14/35] tcg: Move vec_gen_* declarations to tcg-internal.h Richard Henderson
2023-11-07 2:48 ` [PATCH 15/35] tcg: Move tcg_gen_opN " Richard Henderson
2023-11-07 2:48 ` [PATCH 16/35] tcg: Unexport tcg_gen_op*_{i32,i64} Richard Henderson
2023-11-07 2:48 ` [PATCH 17/35] tcg: Move tcg_constant_* out of line Richard Henderson
2023-11-07 2:48 ` [PATCH 18/35] tcg: Move tcg_temp_new_*, tcg_global_mem_new_* " Richard Henderson
2023-11-07 2:48 ` [PATCH 19/35] tcg: Move tcg_temp_free_* " Richard Henderson
2023-11-07 2:48 ` [PATCH 20/35] tcg/mips: Split out tcg_out_setcond_int Richard Henderson
2023-11-07 2:48 ` [PATCH 21/35] tcg/mips: Always implement movcond Richard Henderson
2023-11-07 2:48 ` [PATCH 22/35] tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} Richard Henderson
2023-11-07 2:48 ` [PATCH 23/35] tcg/mips: Implement neg opcodes Richard Henderson
2023-11-07 2:48 ` [PATCH 24/35] tcg/loongarch64: " Richard Henderson
2023-11-07 2:48 ` [PATCH 25/35] tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} Richard Henderson
2023-11-07 2:48 ` [PATCH 26/35] tcg: Don't free vector results Richard Henderson
2023-11-07 2:48 ` [PATCH 27/35] tcg/optimize: Pipe OptContext into reset_ts Richard Henderson
2023-11-07 2:48 ` [PATCH 28/35] tcg/optimize: Split out cmp_better_copy Richard Henderson
2023-11-07 2:48 ` [PATCH 29/35] tcg/optimize: Optimize env memory operations Richard Henderson
2023-11-07 2:48 ` [PATCH 30/35] tcg: Eliminate duplicate env store operations Richard Henderson
2023-11-07 2:48 ` [PATCH 31/35] tcg/optimize: Split out arg_new_constant Richard Henderson
2023-11-07 2:48 ` [PATCH 32/35] tcg: Canonicalize subi to addi during opcode generation Richard Henderson
2023-11-07 2:48 ` [PATCH 33/35] tcg/optimize: Canonicalize subi to addi during optimization Richard Henderson
2023-11-07 2:48 ` [PATCH 34/35] tcg/optimize: Canonicalize sub2 with constants to add2 Richard Henderson
2023-11-07 2:48 ` [PATCH 35/35] tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson
2023-11-07 2:55 ` [PULL 00/35] tcg patch queue Richard Henderson
2023-11-07 3:06 ` Stefan Hajnoczi
2023-11-07 4:59 ` [PATCH " Stefan Hajnoczi
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