From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 25/85] target/hppa: Pass DisasContext to copy_iaoq_entry
Date: Mon, 6 Nov 2023 19:03:07 -0800 [thread overview]
Message-ID: <20231107030407.8979-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231107030407.8979-1-richard.henderson@linaro.org>
Interface change only, no functional effect.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 39 ++++++++++++++++++++-------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4e0bc48b09..e342cc1d08 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -717,7 +717,8 @@ static target_ureg gva_offset_mask(DisasContext *ctx)
: MAKE_64BIT_MASK(0, 32));
}
-static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
+static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest,
+ target_ureg ival, TCGv_reg vval)
{
if (unlikely(ival == -1)) {
tcg_gen_mov_reg(dest, vval);
@@ -738,8 +739,8 @@ static void gen_excp_1(int exception)
static void gen_excp(DisasContext *ctx, int exception)
{
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
gen_excp_1(exception);
ctx->base.is_jmp = DISAS_NORETURN;
@@ -795,8 +796,8 @@ static void gen_goto_tb(DisasContext *ctx, int which,
tcg_gen_movi_reg(cpu_iaoq_b, b);
tcg_gen_exit_tb(ctx->base.tb, which);
} else {
- copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
- copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var);
tcg_gen_lookup_and_goto_ptr();
}
}
@@ -1752,7 +1753,7 @@ static bool do_dbranch(DisasContext *ctx, target_ureg dest,
{
if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) {
if (link != 0) {
- copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
ctx->iaoq_n = dest;
if (is_n) {
@@ -1762,7 +1763,7 @@ static bool do_dbranch(DisasContext *ctx, target_ureg dest,
nullify_over(ctx);
if (link != 0) {
- copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
if (is_n && use_nullify_skip(ctx)) {
@@ -1860,7 +1861,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
if (ctx->null_cond.c == TCG_COND_NEVER) {
if (link != 0) {
- copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
next = tcg_temp_new();
tcg_gen_mov_reg(next, dest);
@@ -1906,7 +1907,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
tmp = tcg_temp_new();
next = tcg_temp_new();
- copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest);
ctx->iaoq_n = -1;
ctx->iaoq_n_var = next;
@@ -2643,8 +2644,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
nullify_over(ctx);
/* Advance the instruction queue. */
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */
@@ -3433,7 +3434,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
load_spr(ctx, new_spc, a->sp);
if (a->l) {
- copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f);
}
if (a->n && use_nullify_skip(ctx)) {
@@ -3442,7 +3443,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
tcg_gen_mov_i64(cpu_iasq_f, new_spc);
tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f);
} else {
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
@@ -3556,14 +3557,14 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a)
nullify_over(ctx);
dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b));
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
- copy_iaoq_entry(cpu_iaoq_b, -1, dest);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest);
tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest));
if (a->l) {
- copy_iaoq_entry(cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var);
}
nullify_set(ctx, a->n);
tcg_gen_lookup_and_goto_ptr();
@@ -4218,7 +4219,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
case DISAS_IAQ_N_STALE_EXIT:
if (ctx->iaoq_f == -1) {
tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
#ifndef CONFIG_USER_ONLY
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
#endif
@@ -4247,8 +4248,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
case DISAS_TOO_MANY:
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
/* FALLTHRU */
case DISAS_IAQ_N_UPDATED:
--
2.34.1
next prev parent reply other threads:[~2023-11-07 3:06 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-07 3:02 [PULL 00/85] target/hppa patch queue Richard Henderson
2023-11-07 3:02 ` [PULL 01/85] target/hppa: Include PSW_P in tb flags and mmu index Richard Henderson
2023-11-07 3:02 ` [PULL 02/85] target/hppa: Rename hppa_tlb_entry to HPPATLBEntry Richard Henderson
2023-11-07 3:02 ` [PULL 03/85] target/hppa: Use IntervalTreeNode in HPPATLBEntry Richard Henderson
2023-11-07 3:02 ` [PULL 04/85] target/hppa: Always report one page to tlb_set_page Richard Henderson
2023-11-07 3:02 ` [PULL 05/85] target/hppa: Split out hppa_flush_tlb_range Richard Henderson
2023-11-07 3:02 ` [PULL 06/85] target/hppa: Populate an interval tree with valid tlb entries Richard Henderson
2023-11-07 3:02 ` [PULL 07/85] target/hppa: Remove get_temp Richard Henderson
2023-11-07 3:02 ` [PULL 08/85] target/hppa: Remove get_temp_tl Richard Henderson
2023-11-07 3:02 ` [PULL 09/85] target/hppa: Remove load_const Richard Henderson
2023-11-07 3:02 ` [PULL 10/85] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-11-07 3:02 ` [PULL 11/85] target/hppa: Fix load in do_load_32 Richard Henderson
2023-11-07 3:02 ` [PULL 12/85] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-11-07 3:02 ` [PULL 13/85] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-11-07 3:02 ` [PULL 14/85] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-11-07 3:02 ` [PULL 15/85] target/hppa: Fix bb_sar " Richard Henderson
2023-11-07 3:02 ` [PULL 16/85] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-11-07 3:02 ` [PULL 17/85] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-11-07 3:03 ` [PULL 18/85] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-11-07 3:03 ` [PULL 19/85] target/hppa: Implement cpu_list Richard Henderson
2023-11-07 3:03 ` [PULL 20/85] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-11-07 3:03 ` [PULL 21/85] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-11-07 3:03 ` [PULL 22/85] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-11-07 3:03 ` [PULL 23/85] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-11-07 3:03 ` [PULL 24/85] target/hppa: Fix hppa64 addressing Richard Henderson
2023-11-07 3:03 ` Richard Henderson [this message]
2023-11-07 3:03 ` [PULL 26/85] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] Richard Henderson
2023-11-07 3:03 ` [PULL 27/85] target/hppa: Use copy_iaoq_entry for link in do_ibranch Richard Henderson
2023-11-07 3:03 ` [PULL 28/85] target/hppa: Mask inputs in copy_iaoq_entry Richard Henderson
2023-11-07 3:03 ` [PULL 29/85] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-11-07 3:03 ` [PULL 30/85] target/hppa: Pass d to do_cond Richard Henderson
2023-11-07 3:03 ` [PULL 31/85] target/hppa: Pass d to do_sub_cond Richard Henderson
2023-11-07 3:03 ` [PULL 32/85] target/hppa: Pass d to do_log_cond Richard Henderson
2023-11-07 3:03 ` [PULL 33/85] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-11-07 3:03 ` [PULL 34/85] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-11-07 3:03 ` [PULL 35/85] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-11-07 3:03 ` [PULL 36/85] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-11-07 3:03 ` [PULL 37/85] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-11-07 3:03 ` [PULL 38/85] target/hppa: Decode d for logical instructions Richard Henderson
2023-11-07 3:03 ` [PULL 39/85] target/hppa: Decode d for unit instructions Richard Henderson
2023-11-07 3:03 ` [PULL 40/85] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-11-07 3:03 ` [PULL 41/85] target/hppa: Decode d for add instructions Richard Henderson
2023-11-07 3:03 ` [PULL 42/85] target/hppa: Decode d for sub instructions Richard Henderson
2023-11-07 3:03 ` [PULL 43/85] target/hppa: Decode d for bb instructions Richard Henderson
2023-11-07 3:03 ` [PULL 44/85] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-11-07 3:03 ` [PULL 45/85] target/hppa: Decode CMPIB double-word Richard Henderson
2023-11-07 3:03 ` [PULL 46/85] target/hppa: Decode ADDB double-word Richard Henderson
2023-11-07 3:03 ` [PULL 47/85] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-11-07 3:03 ` [PULL 48/85] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-11-07 3:03 ` [PULL 49/85] target/hppa: Implement EXTRD Richard Henderson
2023-11-07 3:03 ` [PULL 50/85] target/hppa: Implement SHRPD Richard Henderson
2023-11-07 3:03 ` [PULL 51/85] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-11-07 3:03 ` [PULL 52/85] target/hppa: Implement STDBY Richard Henderson
2023-11-07 3:03 ` [PULL 53/85] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-11-09 15:13 ` Peter Maydell
2023-11-07 3:03 ` [PULL 54/85] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-11-07 3:03 ` [PULL 55/85] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-11-07 3:03 ` [PULL 56/85] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-11-07 3:03 ` [PULL 57/85] target/hppa: Remove remaining " Richard Henderson
2023-11-07 3:03 ` [PULL 58/85] target/hppa: Adjust vmstate_env for pa2.0 tlb Richard Henderson
2023-11-07 3:03 ` [PULL 59/85] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-11-07 3:03 ` [PULL 60/85] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-11-07 3:03 ` [PULL 61/85] target/hppa: Implement HADD Richard Henderson
2023-11-07 3:03 ` [PULL 62/85] target/hppa: Implement HSUB Richard Henderson
2023-11-07 3:03 ` [PULL 63/85] target/hppa: Implement HAVG Richard Henderson
2023-11-07 3:03 ` [PULL 64/85] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-11-07 3:03 ` [PULL 65/85] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-11-07 3:03 ` [PULL 66/85] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-11-07 3:03 ` [PULL 67/85] target/hppa: Implement PERMH Richard Henderson
2023-11-07 3:03 ` [PULL 68/85] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-11-07 3:03 ` [PULL 69/85] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-11-07 3:03 ` [PULL 70/85] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-11-07 3:03 ` [PULL 71/85] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-11-07 3:03 ` [PULL 72/85] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-11-07 3:03 ` [PULL 73/85] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
2023-11-07 3:03 ` [PULL 74/85] target/hppa: Implement pa2.0 data prefetch instructions Richard Henderson
2023-11-07 3:03 ` [PULL 75/85] target/hppa: Add pa2.0 cpu local tlb flushes Richard Henderson
2023-11-09 15:12 ` Peter Maydell
2023-11-07 3:03 ` [PULL 76/85] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system Richard Henderson
2023-11-07 3:03 ` [PULL 77/85] target/hppa: Clear upper bits in mtctl for pa1.x Richard Henderson
2023-11-07 3:04 ` [PULL 78/85] target/hppa: Add unwind_breg to CPUHPPAState Richard Henderson
2023-11-07 3:04 ` [PULL 79/85] target/hppa: Create raise_exception_with_ior Richard Henderson
2023-11-07 3:04 ` [PULL 80/85] target/hppa: Update IIAOQ, IIASQ for pa2.0 Richard Henderson
2023-11-07 3:04 ` [PULL 81/85] target/hppa: Improve interrupt logging Richard Henderson
2023-11-07 3:04 ` [PULL 82/85] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region Richard Henderson
2023-11-07 3:04 ` [PULL 83/85] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory Richard Henderson
2023-11-07 3:04 ` [PULL 84/85] hw/hppa: Turn on 64-bit CPU for C3700 machine Richard Henderson
2023-11-07 3:04 ` [PULL 85/85] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only Richard Henderson
2023-11-07 9:36 ` [PULL 00/85] target/hppa patch queue Stefan Hajnoczi
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