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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/85] target/hppa: Rename hppa_tlb_entry to HPPATLBEntry
Date: Mon,  6 Nov 2023 19:02:44 -0800	[thread overview]
Message-ID: <20231107030407.8979-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231107030407.8979-1-richard.henderson@linaro.org>

Rename to CamelCase per coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/cpu.h        |  8 ++++----
 target/hppa/machine.c    |  6 +++---
 target/hppa/mem_helper.c | 30 +++++++++++++++---------------
 3 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 48d735929e..22edfc955d 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -174,7 +174,7 @@ typedef int64_t  target_sreg;
 #define TREG_FMT_ld   "%"PRId64
 #endif
 
-typedef struct {
+typedef struct HPPATLBEntry {
     uint64_t va_b;
     uint64_t va_e;
     target_ureg pa;
@@ -188,7 +188,7 @@ typedef struct {
     unsigned ar_pl2 : 2;
     unsigned entry_valid : 1;
     unsigned access_id : 16;
-} hppa_tlb_entry;
+} HPPATLBEntry;
 
 typedef struct CPUArchState {
     target_ureg iaoq_f;      /* front */
@@ -234,7 +234,7 @@ typedef struct CPUArchState {
 
     /* ??? Implement a unified itlb/dtlb for the moment.  */
     /* ??? We should use a more intelligent data structure.  */
-    hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
+    HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
     uint32_t tlb_last;
 } CPUHPPAState;
 
@@ -362,7 +362,7 @@ void hppa_cpu_do_interrupt(CPUState *cpu);
 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
                               int type, hwaddr *pphys, int *pprot,
-                              hppa_tlb_entry **tlb_entry);
+                              HPPATLBEntry **tlb_entry);
 extern const MemoryRegionOps hppa_io_eir_ops;
 extern const VMStateDescription vmstate_hppa_cpu;
 void hppa_cpu_alarm_timer(void *);
diff --git a/target/hppa/machine.c b/target/hppa/machine.c
index 905991d7f9..1d3f9b639d 100644
--- a/target/hppa/machine.c
+++ b/target/hppa/machine.c
@@ -69,7 +69,7 @@ static const VMStateInfo vmstate_psw = {
 static int get_tlb(QEMUFile *f, void *opaque, size_t size,
                    const VMStateField *field)
 {
-    hppa_tlb_entry *ent = opaque;
+    HPPATLBEntry *ent = opaque;
     uint32_t val;
 
     memset(ent, 0, sizeof(*ent));
@@ -95,7 +95,7 @@ static int get_tlb(QEMUFile *f, void *opaque, size_t size,
 static int put_tlb(QEMUFile *f, void *opaque, size_t size,
                    const VMStateField *field, JSONWriter *vmdesc)
 {
-    hppa_tlb_entry *ent = opaque;
+    HPPATLBEntry *ent = opaque;
     uint32_t val = 0;
 
     if (ent->entry_valid) {
@@ -153,7 +153,7 @@ static VMStateField vmstate_env_fields[] = {
     VMSTATE_UINT32(fr0_shadow, CPUHPPAState),
 
     VMSTATE_ARRAY(tlb, CPUHPPAState, ARRAY_SIZE(((CPUHPPAState *)0)->tlb),
-                  0, vmstate_tlb, hppa_tlb_entry),
+                  0, vmstate_tlb, HPPATLBEntry),
     VMSTATE_UINT32(tlb_last, CPUHPPAState),
 
     VMSTATE_END_OF_LIST()
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 729032288d..a22de81a48 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -25,12 +25,12 @@
 #include "hw/core/cpu.h"
 #include "trace.h"
 
-static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
+static HPPATLBEntry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
 {
     int i;
 
     for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) {
-        hppa_tlb_entry *ent = &env->tlb[i];
+        HPPATLBEntry *ent = &env->tlb[i];
         if (ent->va_b <= addr && addr <= ent->va_e) {
             trace_hppa_tlb_find_entry(env, ent + i, ent->entry_valid,
                                       ent->va_b, ent->va_e, ent->pa);
@@ -41,7 +41,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
     return NULL;
 }
 
-static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent,
+static void hppa_flush_tlb_ent(CPUHPPAState *env, HPPATLBEntry *ent,
                                bool force_flush_btlb)
 {
     CPUState *cs = env_cpu(env);
@@ -65,9 +65,9 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent,
     ent->va_b = -1;
 }
 
-static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env)
+static HPPATLBEntry *hppa_alloc_tlb_ent(CPUHPPAState *env)
 {
-    hppa_tlb_entry *ent;
+    HPPATLBEntry *ent;
     uint32_t i;
 
     if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >= ARRAY_SIZE(env->tlb)) {
@@ -86,11 +86,11 @@ static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env)
 
 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
                               int type, hwaddr *pphys, int *pprot,
-                              hppa_tlb_entry **tlb_entry)
+                              HPPATLBEntry **tlb_entry)
 {
     hwaddr phys;
     int prot, r_prot, w_prot, x_prot, priv;
-    hppa_tlb_entry *ent;
+    HPPATLBEntry *ent;
     int ret = -1;
 
     if (tlb_entry) {
@@ -231,7 +231,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
 {
     HPPACPU *cpu = HPPA_CPU(cs);
     CPUHPPAState *env = &cpu->env;
-    hppa_tlb_entry *ent;
+    HPPATLBEntry *ent;
     int prot, excp, a_prot;
     hwaddr phys;
 
@@ -275,12 +275,12 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
 /* Insert (Insn/Data) TLB Address.  Note this is PA 1.1 only.  */
 void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
 {
-    hppa_tlb_entry *empty = NULL;
+    HPPATLBEntry *empty = NULL;
     int i;
 
     /* Zap any old entries covering ADDR; notice empty entries on the way.  */
     for (i = HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) {
-        hppa_tlb_entry *ent = &env->tlb[i];
+        HPPATLBEntry *ent = &env->tlb[i];
         if (ent->va_b <= addr && addr <= ent->va_e) {
             if (ent->entry_valid) {
                 hppa_flush_tlb_ent(env, ent, false);
@@ -303,7 +303,7 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
     trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
 }
 
-static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg reg)
+static void set_access_bits(CPUHPPAState *env, HPPATLBEntry *ent, target_ureg reg)
 {
     ent->access_id = extract32(reg, 1, 18);
     ent->u = extract32(reg, 19, 1);
@@ -321,7 +321,7 @@ static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg
 /* Insert (Insn/Data) TLB Protection.  Note this is PA 1.1 only.  */
 void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
 {
-    hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
+    HPPATLBEntry *ent = hppa_find_tlb(env, addr);
 
     if (unlikely(ent == NULL)) {
         qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n");
@@ -337,7 +337,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
 {
     CPUHPPAState *env = cpu_env(cpu);
     target_ulong addr = (target_ulong) data.target_ptr;
-    hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
+    HPPATLBEntry *ent = hppa_find_tlb(env, addr);
 
     if (ent && ent->entry_valid) {
         hppa_flush_tlb_ent(env, ent, false);
@@ -407,7 +407,7 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr)
 /* Return the ar_type of the TLB at VADDR, or -1.  */
 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr)
 {
-    hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr);
+    HPPATLBEntry *ent = hppa_find_tlb(env, vaddr);
     return ent ? ent->ar_type : -1;
 }
 
@@ -422,7 +422,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
     unsigned int phys_page, len, slot;
     int mmu_idx = cpu_mmu_index(env, 0);
     uintptr_t ra = GETPC();
-    hppa_tlb_entry *btlb;
+    HPPATLBEntry *btlb;
     uint64_t virt_page;
     uint32_t *vaddr;
 
-- 
2.34.1



  parent reply	other threads:[~2023-11-07  3:05 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-07  3:02 [PULL 00/85] target/hppa patch queue Richard Henderson
2023-11-07  3:02 ` [PULL 01/85] target/hppa: Include PSW_P in tb flags and mmu index Richard Henderson
2023-11-07  3:02 ` Richard Henderson [this message]
2023-11-07  3:02 ` [PULL 03/85] target/hppa: Use IntervalTreeNode in HPPATLBEntry Richard Henderson
2023-11-07  3:02 ` [PULL 04/85] target/hppa: Always report one page to tlb_set_page Richard Henderson
2023-11-07  3:02 ` [PULL 05/85] target/hppa: Split out hppa_flush_tlb_range Richard Henderson
2023-11-07  3:02 ` [PULL 06/85] target/hppa: Populate an interval tree with valid tlb entries Richard Henderson
2023-11-07  3:02 ` [PULL 07/85] target/hppa: Remove get_temp Richard Henderson
2023-11-07  3:02 ` [PULL 08/85] target/hppa: Remove get_temp_tl Richard Henderson
2023-11-07  3:02 ` [PULL 09/85] target/hppa: Remove load_const Richard Henderson
2023-11-07  3:02 ` [PULL 10/85] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-11-07  3:02 ` [PULL 11/85] target/hppa: Fix load in do_load_32 Richard Henderson
2023-11-07  3:02 ` [PULL 12/85] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-11-07  3:02 ` [PULL 13/85] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-11-07  3:02 ` [PULL 14/85] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-11-07  3:02 ` [PULL 15/85] target/hppa: Fix bb_sar " Richard Henderson
2023-11-07  3:02 ` [PULL 16/85] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-11-07  3:02 ` [PULL 17/85] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-11-07  3:03 ` [PULL 18/85] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-11-07  3:03 ` [PULL 19/85] target/hppa: Implement cpu_list Richard Henderson
2023-11-07  3:03 ` [PULL 20/85] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-11-07  3:03 ` [PULL 21/85] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-11-07  3:03 ` [PULL 22/85] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-11-07  3:03 ` [PULL 23/85] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-11-07  3:03 ` [PULL 24/85] target/hppa: Fix hppa64 addressing Richard Henderson
2023-11-07  3:03 ` [PULL 25/85] target/hppa: Pass DisasContext to copy_iaoq_entry Richard Henderson
2023-11-07  3:03 ` [PULL 26/85] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] Richard Henderson
2023-11-07  3:03 ` [PULL 27/85] target/hppa: Use copy_iaoq_entry for link in do_ibranch Richard Henderson
2023-11-07  3:03 ` [PULL 28/85] target/hppa: Mask inputs in copy_iaoq_entry Richard Henderson
2023-11-07  3:03 ` [PULL 29/85] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-11-07  3:03 ` [PULL 30/85] target/hppa: Pass d to do_cond Richard Henderson
2023-11-07  3:03 ` [PULL 31/85] target/hppa: Pass d to do_sub_cond Richard Henderson
2023-11-07  3:03 ` [PULL 32/85] target/hppa: Pass d to do_log_cond Richard Henderson
2023-11-07  3:03 ` [PULL 33/85] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-11-07  3:03 ` [PULL 34/85] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-11-07  3:03 ` [PULL 35/85] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-11-07  3:03 ` [PULL 36/85] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-11-07  3:03 ` [PULL 37/85] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-11-07  3:03 ` [PULL 38/85] target/hppa: Decode d for logical instructions Richard Henderson
2023-11-07  3:03 ` [PULL 39/85] target/hppa: Decode d for unit instructions Richard Henderson
2023-11-07  3:03 ` [PULL 40/85] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-11-07  3:03 ` [PULL 41/85] target/hppa: Decode d for add instructions Richard Henderson
2023-11-07  3:03 ` [PULL 42/85] target/hppa: Decode d for sub instructions Richard Henderson
2023-11-07  3:03 ` [PULL 43/85] target/hppa: Decode d for bb instructions Richard Henderson
2023-11-07  3:03 ` [PULL 44/85] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-11-07  3:03 ` [PULL 45/85] target/hppa: Decode CMPIB double-word Richard Henderson
2023-11-07  3:03 ` [PULL 46/85] target/hppa: Decode ADDB double-word Richard Henderson
2023-11-07  3:03 ` [PULL 47/85] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-11-07  3:03 ` [PULL 48/85] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-11-07  3:03 ` [PULL 49/85] target/hppa: Implement EXTRD Richard Henderson
2023-11-07  3:03 ` [PULL 50/85] target/hppa: Implement SHRPD Richard Henderson
2023-11-07  3:03 ` [PULL 51/85] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-11-07  3:03 ` [PULL 52/85] target/hppa: Implement STDBY Richard Henderson
2023-11-07  3:03 ` [PULL 53/85] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-11-09 15:13   ` Peter Maydell
2023-11-07  3:03 ` [PULL 54/85] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-11-07  3:03 ` [PULL 55/85] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-11-07  3:03 ` [PULL 56/85] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-11-07  3:03 ` [PULL 57/85] target/hppa: Remove remaining " Richard Henderson
2023-11-07  3:03 ` [PULL 58/85] target/hppa: Adjust vmstate_env for pa2.0 tlb Richard Henderson
2023-11-07  3:03 ` [PULL 59/85] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-11-07  3:03 ` [PULL 60/85] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-11-07  3:03 ` [PULL 61/85] target/hppa: Implement HADD Richard Henderson
2023-11-07  3:03 ` [PULL 62/85] target/hppa: Implement HSUB Richard Henderson
2023-11-07  3:03 ` [PULL 63/85] target/hppa: Implement HAVG Richard Henderson
2023-11-07  3:03 ` [PULL 64/85] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-11-07  3:03 ` [PULL 65/85] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-11-07  3:03 ` [PULL 66/85] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-11-07  3:03 ` [PULL 67/85] target/hppa: Implement PERMH Richard Henderson
2023-11-07  3:03 ` [PULL 68/85] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-11-07  3:03 ` [PULL 69/85] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-11-07  3:03 ` [PULL 70/85] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-11-07  3:03 ` [PULL 71/85] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-11-07  3:03 ` [PULL 72/85] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-11-07  3:03 ` [PULL 73/85] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
2023-11-07  3:03 ` [PULL 74/85] target/hppa: Implement pa2.0 data prefetch instructions Richard Henderson
2023-11-07  3:03 ` [PULL 75/85] target/hppa: Add pa2.0 cpu local tlb flushes Richard Henderson
2023-11-09 15:12   ` Peter Maydell
2023-11-07  3:03 ` [PULL 76/85] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system Richard Henderson
2023-11-07  3:03 ` [PULL 77/85] target/hppa: Clear upper bits in mtctl for pa1.x Richard Henderson
2023-11-07  3:04 ` [PULL 78/85] target/hppa: Add unwind_breg to CPUHPPAState Richard Henderson
2023-11-07  3:04 ` [PULL 79/85] target/hppa: Create raise_exception_with_ior Richard Henderson
2023-11-07  3:04 ` [PULL 80/85] target/hppa: Update IIAOQ, IIASQ for pa2.0 Richard Henderson
2023-11-07  3:04 ` [PULL 81/85] target/hppa: Improve interrupt logging Richard Henderson
2023-11-07  3:04 ` [PULL 82/85] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region Richard Henderson
2023-11-07  3:04 ` [PULL 83/85] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory Richard Henderson
2023-11-07  3:04 ` [PULL 84/85] hw/hppa: Turn on 64-bit CPU for C3700 machine Richard Henderson
2023-11-07  3:04 ` [PULL 85/85] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only Richard Henderson
2023-11-07  9:36 ` [PULL 00/85] target/hppa patch queue Stefan Hajnoczi

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