* [PULL 00/75] Misc HW/UI patches for 2023-11-07
@ 2023-11-07 12:24 Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h' Philippe Mathieu-Daudé
` (16 more replies)
0 siblings, 17 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé
The following changes since commit bb541a7068d2eee51a9abbe2dedcdf27298b1872:
Merge tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu into staging (2023-11-07 15:01:17 +0800)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/misc-cpus-20231107
for you to fetch changes up to 95a40c44501b5e3b8d1922ea37f30142981b2b34:
dump: Add close fd on error return to avoid resource leak (2023-11-07 13:08:49 +0100)
Few checkpatch warnings in target/i386/hvf/x86_emu.c are deliberately ignored.
----------------------------------------------------------------
Misc hardware patch queue
HW emulation:
- PMBus fixes and tests (Titus)
- IDE fixes and tests (Fiona)
- New ADM1266 sensor (Titus)
- Better error propagation in PCI-ISA i82378 (Philippe)
- Declare SD model QOM types using DEFINE_TYPES macro (Philippe)
Topology:
- Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)
Monitor:
- Synchronize CPU state in 'info lapic' (Dongli Zhang)
QOM:
- Have 'cpu-qom.h' target-agnostic (Philippe)
- Move ArchCPUClass definition to each target's cpu.h (Philippe)
- Call object_class_is_abstract once in cpu_class_by_name (Philippe)
UI:
- Use correct key names in titles on MacOS / SDL2 (Adrian)
MIPS:
- Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)
Nios2:
- Create IRQs *after* vCPU is realized (Philippe)
PPC:
- Restrict KVM objects to system emulation (Philippe)
- Move target-specific definitions out of 'cpu-qom.h' (Philippe)
S390X:
- Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)
X86:
- HVF & KVM cleanups (Philippe)
Various targets:
- Use env_archcpu() to optimize (Philippe)
Misc:
- Few global variable shadowing removed (Philippe)
- Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
- Remove few more 'softmmu' mentions (Philippe)
- Fix and cleanup in vl.c (Akihiko & Marc-André)
- Resource leak fix in dump (Zongmin Zhou)
- MAINTAINERS updates (Thomas, Daniel)
----------------------------------------------------------------
Adrian Wowk (1):
ui/sdl2: use correct key names in win title on mac
Akihiko Odaki (1):
vl: Free machine list
Daniel P. Berrangé (1):
MAINTAINERS: update libvirt devel mailing list address
Dongli Zhang (1):
target/i386/monitor: synchronize cpu state for lapic info
Fiona Ebner (2):
hw/ide: reset: cancel async DMA operation before resetting state
tests/qtest: ahci-test: add test exposing reset issue with pending
callback
Marc-André Lureau (1):
vl: constify default_list
Philippe Mathieu-Daudé (51):
tests/vm/ubuntu.aarch64: Correct comment about TCG specific delay
tests/unit/test-seccomp: Remove mentions of softmmu in test names
accel/tcg: Declare tcg_flush_jmp_cache() in 'exec/tb-flush.h'
accel: Introduce cpu_exec_reset_hold()
accel/tcg: Factor tcg_cpu_reset_hold() out
target: Unify QOM style
target: Mention 'cpu-qom.h' is target agnostic
target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'
target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
target/hexagon: Declare QOM definitions in 'cpu-qom.h'
target/loongarch: Declare QOM definitions in 'cpu-qom.h'
target/nios2: Declare QOM definitions in 'cpu-qom.h'
target/openrisc: Declare QOM definitions in 'cpu-qom.h'
target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'
target/ppc: Use env_archcpu() in helper_book3s_msgsndp()
target/riscv: Use env_archcpu() in [check_]nanbox()
target/s390x: Use env_archcpu() in handle_diag_308()
target/xtensa: Use env_archcpu() in update_c[compare|count]()
target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]()
target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]()
target/i386/hvf: Use CPUState typedef
target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'
target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'
target/i386/kvm: Correct comment in kvm_cpu_realize()
target/mips: Fix MSA BZ/BNZ opcodes displacement
target/mips: Fix TX79 LQ/SQ opcodes
sysemu/kvm: Restrict kvmppc_get_radix_page_info() to ppc targets
hw/ppc/e500: Restrict ppce500_init_mpic_kvm() to KVM
target/ppc: Restrict KVM objects to system emulation
target/ppc: Prohibit target specific KVM prototypes on user emulation
target/ppc: Define powerpc_pm_insn_t in 'internal.h'
target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h'
target/ppc: Move PowerPCCPUClass definition to 'cpu.h'
target/ppc: Move powerpc_excp_t definition to 'cpu.h'
target/ppc: Move powerpc_mmu_t definition to 'cpu.h'
target/ppc: Move powerpc_input_t definition to 'cpu.h'
hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState
hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU*
target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG
target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h'
target/nios2: Create IRQs *after* accelerator vCPU is realized
target: Move ArchCPUClass definition to 'cpu.h'
target/alpha: Tidy up alpha_cpu_class_by_name()
hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()
exec/cpu: Have cpu_exec_realize() return a boolean
hw/cpu: Clean up global variable shadowing
hw/loader: Clean up global variable shadowing in rom_add_file()
hw/isa/i82378: Propagate error if PC_SPEAKER device creation failed
hw/sd: Declare QOM types using DEFINE_TYPES() macro
Thomas Huth (4):
MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section
MAINTAINERS: Add the CAN documentation file to the CAN section
MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine
section
MAINTAINERS: Add more guest-agent related files to the corresponding
section
Titus Rwantare (8):
hw/i2c: pmbus add support for block receive
hw/i2c: pmbus: add vout mode bitfields
hw/i2c: pmbus: add fan support
hw/i2c: pmbus: add VCAP register
hw/sensor: add ADM1266 device model
tests/qtest: add tests for ADM1266
hw/i2c: pmbus: immediately clear faults on request
hw/i2c: pmbus: reset page register for out of range reads
Zhao Liu (3):
hw/i386: Fix comment style in topology.h
tests/unit: Rename test-x86-cpuid.c to test-x86-topo.c
hw/cpu: Update the comments of nr_cores and nr_dies
Zhuocheng Ding (1):
system/cpus: Fix CPUState.nr_cores' calculation
Zongmin Zhou (1):
dump: Add close fd on error return to avoid resource leak
MAINTAINERS | 12 +-
include/exec/cpu-common.h | 3 -
include/exec/tb-flush.h | 2 +
include/hw/core/cpu.h | 20 +-
include/hw/i2c/pmbus_device.h | 17 ++
include/hw/i386/topology.h | 33 +--
include/hw/loader.h | 2 +-
include/hw/ppc/ppc.h | 2 +-
include/hw/s390x/css.h | 2 +-
include/hw/s390x/sclp.h | 5 +-
include/sysemu/accel-ops.h | 1 +
include/sysemu/kvm.h | 1 -
target/alpha/cpu-qom.h | 21 +-
target/alpha/cpu.h | 17 +-
target/arm/cpu-qom.h | 61 +----
target/arm/cpu.h | 49 +++-
target/arm/internals.h | 6 +
target/avr/cpu-qom.h | 20 +-
target/avr/cpu.h | 18 +-
target/cris/cpu-qom.h | 24 +-
target/cris/cpu.h | 20 +-
target/hexagon/cpu-qom.h | 27 ++
target/hexagon/cpu.h | 20 +-
target/hppa/cpu-qom.h | 20 +-
target/hppa/cpu.h | 16 +-
target/i386/cpu-qom.h | 42 +--
target/i386/cpu.h | 43 ++-
target/i386/hvf/x86_emu.h | 4 +-
target/loongarch/cpu-qom.h | 23 ++
target/loongarch/cpu.h | 14 +-
target/m68k/cpu-qom.h | 21 +-
target/m68k/cpu.h | 17 +-
target/microblaze/cpu-qom.h | 20 +-
target/microblaze/cpu.h | 15 +-
target/mips/cpu-qom.h | 23 +-
target/mips/cpu.h | 21 +-
target/nios2/cpu-qom.h | 18 ++
target/nios2/cpu.h | 11 +-
target/openrisc/cpu-qom.h | 21 ++
target/openrisc/cpu.h | 14 +-
target/ppc/cpu-qom.h | 164 +----------
target/ppc/cpu.h | 145 +++++++++-
target/ppc/internal.h | 9 +
target/ppc/kvm_ppc.h | 4 +
target/riscv/cpu-qom.h | 26 +-
target/riscv/cpu.h | 26 +-
target/riscv/internals.h | 8 +-
target/rx/cpu-qom.h | 20 +-
target/rx/cpu.h | 18 +-
target/s390x/cpu-qom.h | 41 +--
target/s390x/cpu.h | 45 +++-
target/s390x/cpu_models.h | 8 +-
target/sh4/cpu-qom.h | 28 +-
target/sh4/cpu.h | 24 +-
target/sparc/cpu-qom.h | 23 +-
target/sparc/cpu.h | 22 +-
target/tricore/cpu-qom.h | 15 +-
target/tricore/cpu.h | 10 +-
target/xtensa/cpu-qom.h | 26 +-
target/xtensa/cpu.h | 24 +-
target/mips/tcg/msa.decode | 4 +-
target/mips/tcg/tx79.decode | 2 +-
accel/stubs/tcg-stub.c | 4 -
accel/tcg/cputlb.c | 1 +
accel/tcg/tcg-accel-ops.c | 9 +
accel/tcg/translate-all.c | 8 -
accel/tcg/user-exec-stub.c | 4 +
bsd-user/main.c | 2 +-
cpu-common.c | 6 +-
cpu-target.c | 6 +-
dump/dump.c | 1 +
hw/core/cpu-common.c | 19 +-
hw/core/loader.c | 4 +-
hw/i2c/pmbus_device.c | 237 +++++++++++++++-
hw/ide/core.c | 14 +-
hw/isa/i82378.c | 4 +-
hw/ppc/e500.c | 4 +
hw/s390x/css.c | 3 +-
hw/s390x/sclp.c | 7 +-
hw/sd/aspeed_sdhci.c | 19 +-
hw/sd/bcm2835_sdhost.c | 33 +--
hw/sd/cadence_sdhci.c | 21 +-
hw/sd/core.c | 19 +-
hw/sd/npcm7xx_sdhci.c | 21 +-
hw/sd/pl181.c | 35 ++-
hw/sd/pxa2xx_mmci.c | 35 ++-
hw/sd/sd.c | 37 ++-
hw/sd/sdhci-pci.c | 25 +-
hw/sd/ssi-sd.c | 19 +-
hw/sensor/adm1266.c | 254 ++++++++++++++++++
linux-user/main.c | 2 +-
plugins/core.c | 1 -
system/cpus.c | 9 +-
system/vl.c | 5 +-
target/alpha/cpu.c | 10 +-
target/arm/cpu.c | 3 +-
target/avr/cpu.c | 3 +-
target/cris/cpu.c | 3 +-
target/hexagon/cpu.c | 3 +-
target/i386/cpu.c | 9 +-
target/i386/hvf/hvf.c | 4 +-
target/i386/hvf/x86_emu.c | 111 ++++----
target/i386/kvm/kvm-cpu.c | 1 +
target/i386/monitor.c | 5 +
target/loongarch/cpu.c | 3 +-
target/m68k/cpu.c | 3 +-
target/nios2/cpu.c | 16 +-
target/openrisc/cpu.c | 3 +-
target/ppc/excp_helper.c | 2 +-
target/ppc/kvm-stub.c | 19 --
target/ppc/kvm.c | 4 +-
target/riscv/cpu.c | 3 +-
target/rx/cpu.c | 6 +-
target/s390x/cpu_models.c | 2 +-
target/s390x/diag.c | 2 +-
target/s390x/kvm/kvm.c | 6 +-
target/s390x/tcg/misc_helper.c | 5 +-
target/sh4/cpu.c | 3 -
target/tricore/cpu.c | 3 +-
target/xtensa/cpu.c | 3 +-
target/xtensa/op_helper.c | 4 +-
tests/qtest/adm1266-test.c | 122 +++++++++
tests/qtest/ahci-test.c | 86 +++++-
tests/qtest/max34451-test.c | 24 ++
tests/unit/test-seccomp.c | 24 +-
.../{test-x86-cpuid.c => test-x86-topo.c} | 2 +-
ui/sdl2.c | 8 +
hw/arm/Kconfig | 1 +
hw/sensor/Kconfig | 5 +
hw/sensor/meson.build | 1 +
target/ppc/meson.build | 2 +-
tests/qtest/meson.build | 1 +
tests/unit/meson.build | 4 +-
tests/vm/ubuntu.aarch64 | 2 +-
134 files changed, 1722 insertions(+), 1085 deletions(-)
create mode 100644 target/hexagon/cpu-qom.h
create mode 100644 target/loongarch/cpu-qom.h
create mode 100644 target/nios2/cpu-qom.h
create mode 100644 target/openrisc/cpu-qom.h
create mode 100644 hw/sensor/adm1266.c
delete mode 100644 target/ppc/kvm-stub.c
create mode 100644 tests/qtest/adm1266-test.c
rename tests/unit/{test-x86-cpuid.c => test-x86-topo.c} (99%)
--
2.41.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 37/75] target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h' Philippe Mathieu-Daudé
` (15 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson,
Cédric Le Goater, Nicholas Piggin, Daniel Henrique Barboza
PM instructions are only used by TCG helpers. No need to
expose to other hardware.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-3-philmd@linaro.org>
---
target/ppc/cpu-qom.h | 10 ----------
target/ppc/internal.h | 9 +++++++++
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 41df51269b..f681bfb4a6 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -114,16 +114,6 @@ enum powerpc_excp_t {
POWERPC_EXCP_POWER10,
};
-/*****************************************************************************/
-/* PM instructions */
-typedef enum {
- PPC_PM_DOZE,
- PPC_PM_NAP,
- PPC_PM_SLEEP,
- PPC_PM_RVWINKLE,
- PPC_PM_STOP,
-} powerpc_pm_insn_t;
-
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t powerpc_input_t;
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index c881c67a8b..5b20ecbd33 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -20,6 +20,15 @@
#include "hw/registerfields.h"
+/* PM instructions */
+typedef enum {
+ PPC_PM_DOZE,
+ PPC_PM_NAP,
+ PPC_PM_SLEEP,
+ PPC_PM_RVWINKLE,
+ PPC_PM_STOP,
+} powerpc_pm_insn_t;
+
#define FUNC_MASK(name, ret_type, size, max_val) \
static inline ret_type name(uint##size##_t start, \
uint##size##_t end) \
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 37/75] target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h' Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 38/75] target/ppc: Move PowerPCCPUClass definition " Philippe Mathieu-Daudé
` (14 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson,
Cédric Le Goater, Nicholas Piggin, Daniel Henrique Barboza
ppc_cpu_class_by_name() is only called in target/ppc/,
no need to expose outside (in particular to hw/).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-4-philmd@linaro.org>
---
target/ppc/cpu-qom.h | 2 --
target/ppc/cpu.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index f681bfb4a6..0b8dfa5fee 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -36,8 +36,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
-ObjectClass *ppc_cpu_class_by_name(const char *name);
-
typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 02619e5d54..f3ddfd7a26 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1342,6 +1342,7 @@ struct ArchCPU {
};
+ObjectClass *ppc_cpu_class_by_name(const char *name);
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 38/75] target/ppc: Move PowerPCCPUClass definition to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h' Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 37/75] target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h' Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 39/75] target/ppc: Move powerpc_excp_t " Philippe Mathieu-Daudé
` (13 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson, Nicholas Piggin,
Daniel Henrique Barboza, Cédric Le Goater
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares the
PowerPCCPUClass type. This forward declaration is sufficient
for code in hw/ to use the QOM definitions. No need to expose
the structure definition. Keep it local to target/ppc/ by
moving it to target/ppc/cpu.h.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013125630.95116-5-philmd@linaro.org>
---
include/hw/ppc/ppc.h | 2 +-
target/ppc/cpu-qom.h | 56 --------------------------------------------
target/ppc/cpu.h | 51 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 52 insertions(+), 57 deletions(-)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 17a8dfc107..d5d119ea7f 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -1,7 +1,7 @@
#ifndef HW_PPC_H
#define HW_PPC_H
-#include "target/ppc/cpu-qom.h"
+#include "target/ppc/cpu.h"
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 0b8dfa5fee..65a640470f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_PPC_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#ifdef TARGET_PPC64
#define TYPE_POWERPC_CPU "powerpc64-cpu"
@@ -36,10 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
-typedef struct CPUArchState CPUPPCState;
-typedef struct ppc_tb_t ppc_tb_t;
-typedef struct ppc_dcr_t ppc_dcr_t;
-
/*****************************************************************************/
/* MMU model */
typedef enum powerpc_mmu_t powerpc_mmu_t;
@@ -133,57 +128,6 @@ enum powerpc_input_t {
PPC_FLAGS_INPUT_RCPU,
};
-typedef struct PPCHash64Options PPCHash64Options;
-
-/**
- * PowerPCCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A PowerPC CPU model.
- */
-struct PowerPCCPUClass {
- /*< private >*/
- CPUClass parent_class;
- /*< public >*/
-
- DeviceRealize parent_realize;
- DeviceUnrealize parent_unrealize;
- ResettablePhases parent_phases;
- void (*parent_parse_features)(const char *type, char *str, Error **errp);
-
- uint32_t pvr;
- /*
- * If @best is false, match if pcc is in the family of pvr
- * Else match only if pcc is the best match for pvr in this family.
- */
- bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
- uint64_t pcr_mask; /* Available bits in PCR register */
- uint64_t pcr_supported; /* Bits for supported PowerISA versions */
- uint32_t svr;
- uint64_t insns_flags;
- uint64_t insns_flags2;
- uint64_t msr_mask;
- uint64_t lpcr_mask; /* Available bits in the LPCR */
- uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
- powerpc_mmu_t mmu_model;
- powerpc_excp_t excp_model;
- powerpc_input_t bus_model;
- uint32_t flags;
- int bfd_mach;
- uint32_t l1_dcache_size, l1_icache_size;
-#ifndef CONFIG_USER_ONLY
- unsigned int gdb_num_sprs;
- const char *gdb_spr_xml;
-#endif
- const PPCHash64Options *hash64_opts;
- struct ppc_radix_page_info *radix_page_info;
- uint32_t lrg_decr_bits;
- int n_host_threads;
- void (*init_proc)(CPUPPCState *env);
- int (*check_pow)(CPUPPCState *env);
-};
-
#ifndef CONFIG_USER_ONLY
typedef struct PPCTimebase {
uint64_t guest_timebase;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f3ddfd7a26..55330d9319 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -200,9 +200,14 @@ typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
/* Types used to describe some PowerPC registers etc. */
typedef struct DisasContext DisasContext;
+typedef struct ppc_dcr_t ppc_dcr_t;
typedef struct ppc_spr_t ppc_spr_t;
+typedef struct ppc_tb_t ppc_tb_t;
typedef union ppc_tlb_t ppc_tlb_t;
typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
+typedef struct PPCHash64Options PPCHash64Options;
+
+typedef struct CPUArchState CPUPPCState;
/* SPR access micro-ops generations callbacks */
struct ppc_spr_t {
@@ -1341,6 +1346,52 @@ struct ArchCPU {
int32_t mig_slb_nr;
};
+/**
+ * PowerPCCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A PowerPC CPU model.
+ */
+struct PowerPCCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ DeviceUnrealize parent_unrealize;
+ ResettablePhases parent_phases;
+ void (*parent_parse_features)(const char *type, char *str, Error **errp);
+
+ uint32_t pvr;
+ /*
+ * If @best is false, match if pcc is in the family of pvr
+ * Else match only if pcc is the best match for pvr in this family.
+ */
+ bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
+ uint64_t pcr_mask; /* Available bits in PCR register */
+ uint64_t pcr_supported; /* Bits for supported PowerISA versions */
+ uint32_t svr;
+ uint64_t insns_flags;
+ uint64_t insns_flags2;
+ uint64_t msr_mask;
+ uint64_t lpcr_mask; /* Available bits in the LPCR */
+ uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
+ uint32_t flags;
+ int bfd_mach;
+ uint32_t l1_dcache_size, l1_icache_size;
+#ifndef CONFIG_USER_ONLY
+ unsigned int gdb_num_sprs;
+ const char *gdb_spr_xml;
+#endif
+ const PPCHash64Options *hash64_opts;
+ struct ppc_radix_page_info *radix_page_info;
+ uint32_t lrg_decr_bits;
+ int n_host_threads;
+ void (*init_proc)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
+};
ObjectClass *ppc_cpu_class_by_name(const char *name);
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 39/75] target/ppc: Move powerpc_excp_t definition to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-11-07 12:24 ` [PULL 38/75] target/ppc: Move PowerPCCPUClass definition " Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 40/75] target/ppc: Move powerpc_mmu_t " Philippe Mathieu-Daudé
` (12 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson,
Cédric Le Goater, Nicholas Piggin, Daniel Henrique Barboza
The powerpc_excp_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-6-philmd@linaro.org>
---
target/ppc/cpu-qom.h | 29 -----------------------------
target/ppc/cpu.h | 27 +++++++++++++++++++++++++++
2 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 65a640470f..acc5f1a1dc 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -78,35 +78,6 @@ static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
return mmu_model & POWERPC_MMU_64;
}
-/*****************************************************************************/
-/* Exception model */
-typedef enum powerpc_excp_t powerpc_excp_t;
-enum powerpc_excp_t {
- POWERPC_EXCP_UNKNOWN = 0,
- /* Standard PowerPC exception model */
- POWERPC_EXCP_STD,
- /* PowerPC 40x exception model */
- POWERPC_EXCP_40x,
- /* PowerPC 603/604/G2 exception model */
- POWERPC_EXCP_6xx,
- /* PowerPC 7xx exception model */
- POWERPC_EXCP_7xx,
- /* PowerPC 74xx exception model */
- POWERPC_EXCP_74xx,
- /* BookE exception model */
- POWERPC_EXCP_BOOKE,
- /* PowerPC 970 exception model */
- POWERPC_EXCP_970,
- /* POWER7 exception model */
- POWERPC_EXCP_POWER7,
- /* POWER8 exception model */
- POWERPC_EXCP_POWER8,
- /* POWER9 exception model */
- POWERPC_EXCP_POWER9,
- /* POWER10 exception model */
- POWERPC_EXCP_POWER10,
-};
-
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t powerpc_input_t;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 55330d9319..94a804a605 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -192,6 +192,33 @@ enum {
POWERPC_EXCP_TRAP = 0x40,
};
+/* Exception model */
+typedef enum powerpc_excp_t {
+ POWERPC_EXCP_UNKNOWN = 0,
+ /* Standard PowerPC exception model */
+ POWERPC_EXCP_STD,
+ /* PowerPC 40x exception model */
+ POWERPC_EXCP_40x,
+ /* PowerPC 603/604/G2 exception model */
+ POWERPC_EXCP_6xx,
+ /* PowerPC 7xx exception model */
+ POWERPC_EXCP_7xx,
+ /* PowerPC 74xx exception model */
+ POWERPC_EXCP_74xx,
+ /* BookE exception model */
+ POWERPC_EXCP_BOOKE,
+ /* PowerPC 970 exception model */
+ POWERPC_EXCP_970,
+ /* POWER7 exception model */
+ POWERPC_EXCP_POWER7,
+ /* POWER8 exception model */
+ POWERPC_EXCP_POWER8,
+ /* POWER9 exception model */
+ POWERPC_EXCP_POWER9,
+ /* POWER10 exception model */
+ POWERPC_EXCP_POWER10,
+} powerpc_excp_t;
+
#define PPC_INPUT(env) ((env)->bus_model)
/*****************************************************************************/
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 40/75] target/ppc: Move powerpc_mmu_t definition to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-11-07 12:24 ` [PULL 39/75] target/ppc: Move powerpc_excp_t " Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 41/75] target/ppc: Move powerpc_input_t " Philippe Mathieu-Daudé
` (11 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson,
Cédric Le Goater, Nicholas Piggin, Daniel Henrique Barboza
The powerpc_mmu_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-7-philmd@linaro.org>
---
target/ppc/cpu-qom.h | 43 -------------------------------------------
target/ppc/cpu.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 43 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index acc5f1a1dc..c35374e15f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -35,49 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
-/*****************************************************************************/
-/* MMU model */
-typedef enum powerpc_mmu_t powerpc_mmu_t;
-enum powerpc_mmu_t {
- POWERPC_MMU_UNKNOWN = 0x00000000,
- /* Standard 32 bits PowerPC MMU */
- POWERPC_MMU_32B = 0x00000001,
- /* PowerPC 6xx MMU with software TLB */
- POWERPC_MMU_SOFT_6xx = 0x00000002,
- /*
- * PowerPC 74xx MMU with software TLB (this has been
- * disabled, see git history for more information.
- * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
- */
- POWERPC_MMU_SOFT_74xx = 0x00000003,
- /* PowerPC 4xx MMU with software TLB */
- POWERPC_MMU_SOFT_4xx = 0x00000004,
- /* PowerPC MMU in real mode only */
- POWERPC_MMU_REAL = 0x00000006,
- /* Freescale MPC8xx MMU model */
- POWERPC_MMU_MPC8xx = 0x00000007,
- /* BookE MMU model */
- POWERPC_MMU_BOOKE = 0x00000008,
- /* BookE 2.06 MMU model */
- POWERPC_MMU_BOOKE206 = 0x00000009,
-#define POWERPC_MMU_64 0x00010000
- /* 64 bits PowerPC MMU */
- POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
- /* Architecture 2.03 and later (has LPCR) */
- POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
- /* Architecture 2.06 variant */
- POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
- /* Architecture 2.07 variant */
- POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
- /* Architecture 3.00 variant */
- POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
-};
-
-static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
-{
- return mmu_model & POWERPC_MMU_64;
-}
-
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t powerpc_input_t;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 94a804a605..d859c45a2e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -219,6 +219,48 @@ typedef enum powerpc_excp_t {
POWERPC_EXCP_POWER10,
} powerpc_excp_t;
+/*****************************************************************************/
+/* MMU model */
+typedef enum powerpc_mmu_t {
+ POWERPC_MMU_UNKNOWN = 0x00000000,
+ /* Standard 32 bits PowerPC MMU */
+ POWERPC_MMU_32B = 0x00000001,
+ /* PowerPC 6xx MMU with software TLB */
+ POWERPC_MMU_SOFT_6xx = 0x00000002,
+ /*
+ * PowerPC 74xx MMU with software TLB (this has been
+ * disabled, see git history for more information.
+ * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
+ */
+ POWERPC_MMU_SOFT_74xx = 0x00000003,
+ /* PowerPC 4xx MMU with software TLB */
+ POWERPC_MMU_SOFT_4xx = 0x00000004,
+ /* PowerPC MMU in real mode only */
+ POWERPC_MMU_REAL = 0x00000006,
+ /* Freescale MPC8xx MMU model */
+ POWERPC_MMU_MPC8xx = 0x00000007,
+ /* BookE MMU model */
+ POWERPC_MMU_BOOKE = 0x00000008,
+ /* BookE 2.06 MMU model */
+ POWERPC_MMU_BOOKE206 = 0x00000009,
+#define POWERPC_MMU_64 0x00010000
+ /* 64 bits PowerPC MMU */
+ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
+ /* Architecture 2.03 and later (has LPCR) */
+ POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
+ /* Architecture 2.06 variant */
+ POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
+ /* Architecture 2.07 variant */
+ POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
+ /* Architecture 3.00 variant */
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
+} powerpc_mmu_t;
+
+static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
+{
+ return mmu_model & POWERPC_MMU_64;
+}
+
#define PPC_INPUT(env) ((env)->bus_model)
/*****************************************************************************/
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 41/75] target/ppc: Move powerpc_input_t definition to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2023-11-07 12:24 ` [PULL 40/75] target/ppc: Move powerpc_mmu_t " Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 42/75] hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState Philippe Mathieu-Daudé
` (10 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson,
Cédric Le Goater, Nicholas Piggin, Daniel Henrique Barboza
The powerpc_input_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-8-philmd@linaro.org>
---
target/ppc/cpu-qom.h | 21 ---------------------
target/ppc/cpu.h | 20 ++++++++++++++++++++
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index c35374e15f..0241609efe 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -35,27 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
-/*****************************************************************************/
-/* Input pins model */
-typedef enum powerpc_input_t powerpc_input_t;
-enum powerpc_input_t {
- PPC_FLAGS_INPUT_UNKNOWN = 0,
- /* PowerPC 6xx bus */
- PPC_FLAGS_INPUT_6xx,
- /* BookE bus */
- PPC_FLAGS_INPUT_BookE,
- /* PowerPC 405 bus */
- PPC_FLAGS_INPUT_405,
- /* PowerPC 970 bus */
- PPC_FLAGS_INPUT_970,
- /* PowerPC POWER7 bus */
- PPC_FLAGS_INPUT_POWER7,
- /* PowerPC POWER9 bus */
- PPC_FLAGS_INPUT_POWER9,
- /* Freescale RCPU bus */
- PPC_FLAGS_INPUT_RCPU,
-};
-
#ifndef CONFIG_USER_ONLY
typedef struct PPCTimebase {
uint64_t guest_timebase;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d859c45a2e..f8101ffa29 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -261,6 +261,26 @@ static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
return mmu_model & POWERPC_MMU_64;
}
+/*****************************************************************************/
+/* Input pins model */
+typedef enum powerpc_input_t {
+ PPC_FLAGS_INPUT_UNKNOWN = 0,
+ /* PowerPC 6xx bus */
+ PPC_FLAGS_INPUT_6xx,
+ /* BookE bus */
+ PPC_FLAGS_INPUT_BookE,
+ /* PowerPC 405 bus */
+ PPC_FLAGS_INPUT_405,
+ /* PowerPC 970 bus */
+ PPC_FLAGS_INPUT_970,
+ /* PowerPC POWER7 bus */
+ PPC_FLAGS_INPUT_POWER7,
+ /* PowerPC POWER9 bus */
+ PPC_FLAGS_INPUT_POWER9,
+ /* Freescale RCPU bus */
+ PPC_FLAGS_INPUT_RCPU,
+} powerpc_input_t;
+
#define PPC_INPUT(env) ((env)->bus_model)
/*****************************************************************************/
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 42/75] hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2023-11-07 12:24 ` [PULL 41/75] target/ppc: Move powerpc_input_t " Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 43/75] hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU* Philippe Mathieu-Daudé
` (9 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Thomas Huth, Halil Pasic,
Christian Borntraeger, Eric Farman, Richard Henderson,
David Hildenbrand, Ilya Leoshkevich
"hw/s390x/css.h" is a header used by target-agnostic objects
(such hw/s390x/virtio-ccw-gpu.c), thus can not use target-specific
types, such CPUS390XState.
Have css_do_sic() take S390CPU a pointer, which is target-agnostic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-2-philmd@linaro.org>
---
include/hw/s390x/css.h | 2 +-
hw/s390x/css.c | 3 ++-
target/s390x/kvm/kvm.c | 2 +-
target/s390x/tcg/misc_helper.c | 3 ++-
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h
index 75e5381613..ba72ee3dd2 100644
--- a/include/hw/s390x/css.h
+++ b/include/hw/s390x/css.h
@@ -233,7 +233,7 @@ typedef enum {
} CssIoAdapterType;
void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
-int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
+int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode);
uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
uint8_t flags, Error **errp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 95d1b3a3ce..bcedec2fc8 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -644,8 +644,9 @@ void css_conditional_io_interrupt(SubchDev *sch)
}
}
-int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
+int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode)
{
+ CPUS390XState *env = &cpu->env;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
int r;
diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c
index 0f0e784b2a..1ddad0bec1 100644
--- a/target/s390x/kvm/kvm.c
+++ b/target/s390x/kvm/kvm.c
@@ -1358,7 +1358,7 @@ static int kvm_sic_service_call(S390CPU *cpu, struct kvm_run *run)
mode = env->regs[r1] & 0xffff;
isc = (env->regs[r3] >> 27) & 0x7;
- r = css_do_sic(env, isc, mode);
+ r = css_do_sic(cpu, isc, mode);
if (r) {
kvm_s390_program_interrupt(cpu, -r);
}
diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
index e85658ce22..56c7f00cf9 100644
--- a/target/s390x/tcg/misc_helper.c
+++ b/target/s390x/tcg/misc_helper.c
@@ -761,10 +761,11 @@ void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba,
void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint64_t r3)
{
+ S390CPU *cpu = env_archcpu(env);
int r;
qemu_mutex_lock_iothread();
- r = css_do_sic(env, (r3 >> 27) & 0x7, r1 & 0xffff);
+ r = css_do_sic(cpu, (r3 >> 27) & 0x7, r1 & 0xffff);
qemu_mutex_unlock_iothread();
/* css_do_sic() may actually return a PGM_xxx value to inject */
if (r) {
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 43/75] hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU*
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2023-11-07 12:24 ` [PULL 42/75] hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 44/75] target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG Philippe Mathieu-Daudé
` (8 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Thomas Huth, Halil Pasic,
Christian Borntraeger, Eric Farman, Richard Henderson,
David Hildenbrand, Ilya Leoshkevich
"hw/s390x/sclp.h" is a header used by target-agnostic objects
(such hw/char/sclpconsole[-lm].c), thus can not use target-specific
types, such CPUS390XState.
Have sclp_service_call[_protected]() take a S390CPU pointer, which
is target-agnostic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-3-philmd@linaro.org>
---
include/hw/s390x/sclp.h | 5 ++---
hw/s390x/sclp.c | 7 ++++---
target/s390x/kvm/kvm.c | 4 ++--
target/s390x/tcg/misc_helper.c | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/s390x/sclp.h b/include/hw/s390x/sclp.h
index 9aef6d9370..e229b81a67 100644
--- a/include/hw/s390x/sclp.h
+++ b/include/hw/s390x/sclp.h
@@ -227,8 +227,7 @@ static inline int sccb_data_len(SCCB *sccb)
void s390_sclp_init(void);
void sclp_service_interrupt(uint32_t sccb);
void raise_irq_cpu_hotplug(void);
-int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
-int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
- uint32_t code);
+int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code);
+int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code);
#endif
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
index d339cbb7e4..893e71a41b 100644
--- a/hw/s390x/sclp.c
+++ b/hw/s390x/sclp.c
@@ -269,9 +269,9 @@ static void sclp_execute(SCLPDevice *sclp, SCCB *sccb, uint32_t code)
* service_interrupt call.
*/
#define SCLP_PV_DUMMY_ADDR 0x4000
-int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
- uint32_t code)
+int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code)
{
+ CPUS390XState *env = &cpu->env;
SCLPDevice *sclp = get_sclp_device();
SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp);
SCCBHeader header;
@@ -296,8 +296,9 @@ out_write:
return 0;
}
-int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code)
+int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code)
{
+ CPUS390XState *env = &cpu->env;
SCLPDevice *sclp = get_sclp_device();
SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp);
SCCBHeader header;
diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c
index 1ddad0bec1..33ab3551f4 100644
--- a/target/s390x/kvm/kvm.c
+++ b/target/s390x/kvm/kvm.c
@@ -1174,12 +1174,12 @@ static void kvm_sclp_service_call(S390CPU *cpu, struct kvm_run *run,
break;
case ICPT_PV_INSTR:
g_assert(s390_is_pv());
- sclp_service_call_protected(env, sccb, code);
+ sclp_service_call_protected(cpu, sccb, code);
/* Setting the CC is done by the Ultravisor. */
break;
case ICPT_INSTRUCTION:
g_assert(!s390_is_pv());
- r = sclp_service_call(env, sccb, code);
+ r = sclp_service_call(cpu, sccb, code);
if (r < 0) {
kvm_s390_program_interrupt(cpu, -r);
return;
diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
index 56c7f00cf9..6aa7907438 100644
--- a/target/s390x/tcg/misc_helper.c
+++ b/target/s390x/tcg/misc_helper.c
@@ -102,7 +102,7 @@ uint64_t HELPER(stck)(CPUS390XState *env)
uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2)
{
qemu_mutex_lock_iothread();
- int r = sclp_service_call(env, r1, r2);
+ int r = sclp_service_call(env_archcpu(env), r1, r2);
qemu_mutex_unlock_iothread();
if (r < 0) {
tcg_s390_program_interrupt(env, -r, GETPC());
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 44/75] target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2023-11-07 12:24 ` [PULL 43/75] hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU* Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 45/75] target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h' Philippe Mathieu-Daudé
` (7 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Thomas Huth, Richard Henderson,
David Hildenbrand, Ilya Leoshkevich
cpu_get_tb_cpu_state() is TCG specific. Another accelerator
calling it would be a bug, so restrict the definition to TCG,
along with "tcg_s390x.h" header inclusion.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-4-philmd@linaro.org>
---
target/s390x/cpu.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 38d7197f4c..110902fa3c 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -29,7 +29,6 @@
#include "cpu_models.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-#include "tcg/tcg_s390x.h"
#include "qapi/qapi-types-machine-common.h"
#define ELF_MACHINE_UNAME "S390X"
@@ -383,6 +382,10 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
#endif
}
+#ifdef CONFIG_TCG
+
+#include "tcg/tcg_s390x.h"
+
static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
@@ -405,6 +408,8 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
}
}
+#endif /* CONFIG_TCG */
+
/* PER bits from control register 9 */
#define PER_CR9_EVENT_BRANCH 0x80000000
#define PER_CR9_EVENT_IFETCH 0x40000000
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 45/75] target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2023-11-07 12:24 ` [PULL 44/75] target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 47/75] target: Move ArchCPUClass definition " Philippe Mathieu-Daudé
` (6 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Thomas Huth, Richard Henderson,
David Hildenbrand, Ilya Leoshkevich
"target/s390x/cpu-qom.h" has to be target-agnostic. However, it
currently declares CPUS390XState, which is target-specific.
Move that declaration to "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-5-philmd@linaro.org>
---
target/s390x/cpu-qom.h | 2 --
target/s390x/cpu.h | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index fcd70daddf..ccf126b7a9 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -33,8 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;
-typedef struct CPUArchState CPUS390XState;
-
typedef enum cpu_reset_type {
S390_CPU_RESET_NORMAL,
S390_CPU_RESET_INITIAL,
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 110902fa3c..942589c597 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -55,7 +55,7 @@ typedef struct PSW {
uint64_t addr;
} PSW;
-struct CPUArchState {
+typedef struct CPUArchState {
uint64_t regs[16]; /* GP registers */
/*
* The floating point registers are part of the vector registers.
@@ -157,7 +157,7 @@ struct CPUArchState {
/* currently processed sigp order */
uint8_t sigp_order;
-};
+} CPUS390XState;
static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 47/75] target: Move ArchCPUClass definition to 'cpu.h'
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2023-11-07 12:24 ` [PULL 45/75] target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h' Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 51/75] hw/cpu: Clean up global variable shadowing Philippe Mathieu-Daudé
` (5 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Richard Henderson, Peter Maydell,
Michael Rolnik, Edgar E. Iglesias, Brian Cain, Song Gao,
Laurent Vivier, Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo,
Chris Wulff, Marek Vasut, Stafford Horne, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Yoshinori Sato, David Hildenbrand, Ilya Leoshkevich,
Thomas Huth, Mark Cave-Ayland, Artyom Tarasenko,
Bastian Koppelmann, Max Filippov
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
ArchCPUClass type. These forward declarations are sufficient
for code in hw/ to use the QOM definitions. No need to expose
these structure definitions. Keep each local to their target/
by moving them to the corresponding "cpu.h" header.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-13-philmd@linaro.org>
---
target/alpha/cpu-qom.h | 16 ---------------
target/alpha/cpu.h | 13 +++++++++++++
target/arm/cpu-qom.h | 27 -------------------------
target/arm/cpu.h | 25 ++++++++++++++++++++++++
target/avr/cpu-qom.h | 16 ---------------
target/avr/cpu.h | 14 +++++++++++++
target/cris/cpu-qom.h | 19 ------------------
target/cris/cpu.h | 16 +++++++++++++++
target/hexagon/cpu-qom.h | 1 -
target/hppa/cpu-qom.h | 16 ---------------
target/hppa/cpu.h | 14 +++++++++++++
target/i386/cpu-qom.h | 39 -------------------------------------
target/i386/cpu.h | 38 ++++++++++++++++++++++++++++++++++++
target/loongarch/cpu-qom.h | 1 -
target/m68k/cpu-qom.h | 16 ---------------
target/m68k/cpu.h | 13 +++++++++++++
target/microblaze/cpu-qom.h | 16 ---------------
target/microblaze/cpu.h | 13 +++++++++++++
target/mips/cpu-qom.h | 20 -------------------
target/mips/cpu.h | 17 ++++++++++++++++
target/nios2/cpu-qom.h | 1 -
target/openrisc/cpu-qom.h | 1 -
target/riscv/cpu-qom.h | 16 ---------------
target/riscv/cpu.h | 16 +++++++++++++++
target/rx/cpu-qom.h | 15 --------------
target/rx/cpu.h | 14 +++++++++++++
target/s390x/cpu-qom.h | 35 ---------------------------------
target/s390x/cpu.h | 30 ++++++++++++++++++++++++++++
target/s390x/cpu_models.h | 8 ++++----
target/sh4/cpu-qom.h | 23 ----------------------
target/sh4/cpu.h | 20 +++++++++++++++++++
target/sparc/cpu-qom.h | 18 -----------------
target/sparc/cpu.h | 18 +++++++++++++++--
target/tricore/cpu-qom.h | 10 ----------
target/tricore/cpu.h | 6 ++++++
target/xtensa/cpu-qom.h | 21 --------------------
target/xtensa/cpu.h | 20 +++++++++++++++++--
37 files changed, 287 insertions(+), 335 deletions(-)
diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index c4a4523993..1b32b18d34 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_ALPHA_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_ALPHA_CPU "alpha-cpu"
@@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
-/**
- * AlphaCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- *
- * An Alpha CPU model.
- */
-struct AlphaCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- DeviceReset parent_reset;
-};
-
-
#endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 3bff56c565..d672e911dd 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -267,6 +267,19 @@ struct ArchCPU {
QEMUTimer *alarm_timer;
};
+/**
+ * AlphaCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An Alpha CPU model.
+ */
+struct AlphaCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ DeviceReset parent_reset;
+};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_alpha_cpu;
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 35c3b0924e..02b914c876 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_ARM_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_ARM_CPU "arm-cpu"
@@ -29,35 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
-typedef struct ARMCPUInfo {
- const char *name;
- void (*initfn)(Object *obj);
- void (*class_init)(ObjectClass *oc, void *data);
-} ARMCPUInfo;
-
-/**
- * ARMCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * An ARM CPU model.
- */
-struct ARMCPUClass {
- CPUClass parent_class;
-
- const ARMCPUInfo *info;
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
-
#define TYPE_AARCH64_CPU "aarch64-cpu"
typedef struct AArch64CPUClass AArch64CPUClass;
DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU)
-struct AArch64CPUClass {
- ARMCPUClass parent_class;
-};
-
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4a86c8f831..a0282e0d28 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1116,6 +1116,31 @@ struct ArchCPU {
uint64_t gt_cntfrq_hz;
};
+typedef struct ARMCPUInfo {
+ const char *name;
+ void (*initfn)(Object *obj);
+ void (*class_init)(ObjectClass *oc, void *data);
+} ARMCPUInfo;
+
+/**
+ * ARMCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * An ARM CPU model.
+ */
+struct ARMCPUClass {
+ CPUClass parent_class;
+
+ const ARMCPUInfo *info;
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
+struct AArch64CPUClass {
+ ARMCPUClass parent_class;
+};
+
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 75590cdd97..38dbcc0535 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -22,7 +22,6 @@
#define TARGET_AVR_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_AVR_CPU "avr-cpu"
@@ -31,19 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
-/**
- * AVRCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A AVR CPU model.
- */
-struct AVRCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
-
#endif /* TARGET_AVR_CPU_QOM_H */
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 0487399cb2..8a17862737 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -147,6 +147,20 @@ struct ArchCPU {
CPUAVRState env;
};
+/**
+ * AVRCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A AVR CPU model.
+ */
+struct AVRCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
extern const struct VMStateDescription vms_avr_cpu;
void avr_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index d7e5f33e62..741ca97a1b 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_CRIS_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_CRIS_CPU "cris-cpu"
@@ -30,22 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
-/**
- * CRISCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- * @vr: Version Register value.
- *
- * A CRIS CPU model.
- */
-struct CRISCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-
- uint32_t vr;
-};
-
-
#endif
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index b821bb7983..1be7f90319 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -179,6 +179,22 @@ struct ArchCPU {
CPUCRISState env;
};
+/**
+ * CRISCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @vr: Version Register value.
+ *
+ * A CRIS CPU model.
+ */
+struct CRISCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+
+ uint32_t vr;
+};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_cris_cpu;
diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index f02df7ee6f..da92fe7468 100644
--- a/target/hexagon/cpu-qom.h
+++ b/target/hexagon/cpu-qom.h
@@ -10,7 +10,6 @@
#define QEMU_HEXAGON_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_HEXAGON_CPU "hexagon-cpu"
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index b7d9cdfe11..5c454bf543 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -21,26 +21,10 @@
#define QEMU_HPPA_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_HPPA_CPU "hppa-cpu"
#define TYPE_HPPA64_CPU "hppa64-cpu"
OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
-/**
- * HPPACPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- *
- * An HPPA CPU model.
- */
-struct HPPACPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- DeviceReset parent_reset;
-};
-
-
#endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index b39bae00d3..cecec59700 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -253,6 +253,20 @@ struct ArchCPU {
QEMUTimer *alarm_timer;
};
+/**
+ * HPPACPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An HPPA CPU model.
+ */
+struct HPPACPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ DeviceReset parent_reset;
+};
+
#include "exec/cpu-all.h"
static inline bool hppa_is_pa20(CPUHPPAState *env)
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index dffc74c1ce..d4e216d000 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -21,8 +21,6 @@
#define QEMU_I386_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qemu/notify.h"
-#include "qom/object.h"
#ifdef TARGET_X86_64
#define TYPE_X86_CPU "x86_64-cpu"
@@ -35,41 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
-typedef struct X86CPUModel X86CPUModel;
-
-/**
- * X86CPUClass:
- * @cpu_def: CPU model definition
- * @host_cpuid_required: Whether CPU model requires cpuid from host.
- * @ordering: Ordering on the "-cpu help" CPU model list.
- * @migration_safe: See CpuDefinitionInfo::migration_safe
- * @static_model: See CpuDefinitionInfo::static
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * An x86 CPU model or family.
- */
-struct X86CPUClass {
- CPUClass parent_class;
-
- /* CPU definition, automatically loaded by instance_init if not NULL.
- * Should be eventually replaced by subclass-specific property defaults.
- */
- X86CPUModel *model;
-
- bool host_cpuid_required;
- int ordering;
- bool migration_safe;
- bool static_model;
-
- /* Optional description of CPU model.
- * If unavailable, cpu_def->model_id is used */
- const char *model_description;
-
- DeviceRealize parent_realize;
- DeviceUnrealize parent_unrealize;
- ResettablePhases parent_phases;
-};
-
-
#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6c6b066986..0028aeb0ef 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2037,6 +2037,44 @@ struct ArchCPU {
bool xen_vapic;
};
+typedef struct X86CPUModel X86CPUModel;
+
+/**
+ * X86CPUClass:
+ * @cpu_def: CPU model definition
+ * @host_cpuid_required: Whether CPU model requires cpuid from host.
+ * @ordering: Ordering on the "-cpu help" CPU model list.
+ * @migration_safe: See CpuDefinitionInfo::migration_safe
+ * @static_model: See CpuDefinitionInfo::static
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * An x86 CPU model or family.
+ */
+struct X86CPUClass {
+ CPUClass parent_class;
+
+ /*
+ * CPU definition, automatically loaded by instance_init if not NULL.
+ * Should be eventually replaced by subclass-specific property defaults.
+ */
+ X86CPUModel *model;
+
+ bool host_cpuid_required;
+ int ordering;
+ bool migration_safe;
+ bool static_model;
+
+ /*
+ * Optional description of CPU model.
+ * If unavailable, cpu_def->model_id is used.
+ */
+ const char *model_description;
+
+ DeviceRealize parent_realize;
+ DeviceUnrealize parent_unrealize;
+ ResettablePhases parent_phases;
+};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_x86_cpu;
diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
index 82c86d146d..fa3fcf7186 100644
--- a/target/loongarch/cpu-qom.h
+++ b/target/loongarch/cpu-qom.h
@@ -9,7 +9,6 @@
#define LOONGARCH_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index df0cc8b7a3..273e8eae41 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_M68K_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_M68K_CPU "m68k-cpu"
@@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
-/*
- * M68kCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A Motorola 68k CPU model.
- */
-struct M68kCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
-
#endif
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7f34686a6f..6cfc696d2b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -169,6 +169,19 @@ struct ArchCPU {
CPUM68KState env;
};
+/*
+ * M68kCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A Motorola 68k CPU model.
+ */
+struct M68kCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
#ifndef CONFIG_USER_ONLY
void m68k_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index 78f549b57d..92e539fb2f 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -21,25 +21,9 @@
#define QEMU_MICROBLAZE_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
-/**
- * MicroBlazeCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A MicroBlaze CPU model.
- */
-struct MicroBlazeCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
-
#endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e8000237d8..b5374365f5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -355,6 +355,19 @@ struct ArchCPU {
MicroBlazeCPUConfig cfg;
};
+/**
+ * MicroBlazeCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A MicroBlaze CPU model.
+ */
+struct MicroBlazeCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
#ifndef CONFIG_USER_ONLY
void mb_cpu_do_interrupt(CPUState *cs);
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 5822dfb1d2..0eea2a2598 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_MIPS_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#ifdef TARGET_MIPS64
#define TYPE_MIPS_CPU "mips64-cpu"
@@ -34,23 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
-/**
- * MIPSCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A MIPS CPU model.
- */
-struct MIPSCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
- const struct mips_def_t *cpu_def;
-
- /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
- bool no_data_aborts;
-};
-
-
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 12cc1bfafd..52f13f0363 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1217,6 +1217,23 @@ struct ArchCPU {
Clock *count_div; /* Divider for CP0_Count clock */
};
+/**
+ * MIPSCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A MIPS CPU model.
+ */
+struct MIPSCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+ const struct mips_def_t *cpu_def;
+
+ /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
+ bool no_data_aborts;
+};
void mips_cpu_list(void);
diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h
index 931bc69b10..2fd9121540 100644
--- a/target/nios2/cpu-qom.h
+++ b/target/nios2/cpu-qom.h
@@ -10,7 +10,6 @@
#define QEMU_NIOS2_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_NIOS2_CPU "nios2-cpu"
diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h
index 1ba9fb0a4c..14bac33312 100644
--- a/target/openrisc/cpu-qom.h
+++ b/target/openrisc/cpu-qom.h
@@ -10,7 +10,6 @@
#define QEMU_OPENRISC_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_OPENRISC_CPU "or1k-cpu"
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 76efb614a6..91b3361dec 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -20,7 +20,6 @@
#define RISCV_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
@@ -44,21 +43,6 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
-typedef struct CPUArchState CPURISCVState;
-
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
-/**
- * RISCVCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RISCV CPU model.
- */
-struct RISCVCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b49fa17e68..bf58b0f0b5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -32,6 +32,8 @@
#include "qapi/qapi-types-common.h"
#include "cpu-qom.h"
+typedef struct CPUArchState CPURISCVState;
+
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#if defined(TARGET_RISCV32)
@@ -436,6 +438,20 @@ struct ArchCPU {
GHashTable *pmu_event_ctr_map;
};
+/**
+ * RISCVCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A RISCV CPU model.
+ */
+struct RISCVCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
return (env->misa_ext & ext) != 0;
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 6213d877f7..ac2e5785ef 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -20,7 +20,6 @@
#define RX_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_RX_CPU "rx-cpu"
@@ -31,18 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
-/*
- * RXCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RX CPU model.
- */
-struct RXCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
#endif
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index c81613770c..e931e77e85 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -112,6 +112,20 @@ struct ArchCPU {
CPURXState env;
};
+/*
+ * RXCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A RX CPU model.
+ */
+struct RXCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
const char *rx_crname(uint8_t cr);
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index ccf126b7a9..c59bb1eab1 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_S390_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_S390_CPU "s390x-cpu"
@@ -30,38 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
-typedef struct S390CPUModel S390CPUModel;
-typedef struct S390CPUDef S390CPUDef;
-
-typedef enum cpu_reset_type {
- S390_CPU_RESET_NORMAL,
- S390_CPU_RESET_INITIAL,
- S390_CPU_RESET_CLEAR,
-} cpu_reset_type;
-
-/**
- * S390CPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- * @load_normal: Performs a load normal.
- * @cpu_reset: Performs a CPU reset.
- * @initial_cpu_reset: Performs an initial CPU reset.
- *
- * An S/390 CPU model.
- */
-struct S390CPUClass {
- CPUClass parent_class;
-
- const S390CPUDef *cpu_def;
- bool kvm_required;
- bool is_static;
- bool is_migration_safe;
- const char *desc;
-
- DeviceRealize parent_realize;
- DeviceReset parent_reset;
- void (*load_normal)(CPUState *cpu);
- void (*reset)(CPUState *cpu, cpu_reset_type type);
-};
-
#endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 942589c597..fa3aac4f97 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -180,6 +180,36 @@ struct ArchCPU {
uint32_t irqstate_saved_size;
};
+typedef enum cpu_reset_type {
+ S390_CPU_RESET_NORMAL,
+ S390_CPU_RESET_INITIAL,
+ S390_CPU_RESET_CLEAR,
+} cpu_reset_type;
+
+/**
+ * S390CPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ * @load_normal: Performs a load normal.
+ * @cpu_reset: Performs a CPU reset.
+ * @initial_cpu_reset: Performs an initial CPU reset.
+ *
+ * An S/390 CPU model.
+ */
+struct S390CPUClass {
+ CPUClass parent_class;
+
+ const S390CPUDef *cpu_def;
+ bool kvm_required;
+ bool is_static;
+ bool is_migration_safe;
+ const char *desc;
+
+ DeviceRealize parent_realize;
+ DeviceReset parent_reset;
+ void (*load_normal)(CPUState *cpu);
+ void (*reset)(CPUState *cpu, cpu_reset_type type);
+};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_s390_cpu;
diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
index cc7305ec21..d7b8912989 100644
--- a/target/s390x/cpu_models.h
+++ b/target/s390x/cpu_models.h
@@ -18,7 +18,7 @@
#include "hw/core/cpu.h"
/* static CPU definition */
-struct S390CPUDef {
+typedef struct S390CPUDef {
const char *name; /* name exposed to the user */
const char *desc; /* description exposed to the user */
uint8_t gen; /* hw generation identification */
@@ -38,10 +38,10 @@ struct S390CPUDef {
S390FeatBitmap full_feat;
/* used to init full_feat from generated data */
S390FeatInit full_init;
-};
+} S390CPUDef;
/* CPU model based on a CPU definition */
-struct S390CPUModel {
+typedef struct S390CPUModel {
const S390CPUDef *def;
S390FeatBitmap features;
/* values copied from the "host" model, can change during migration */
@@ -49,7 +49,7 @@ struct S390CPUModel {
uint32_t cpu_id; /* CPU id */
uint8_t cpu_id_format; /* CPU id format bit */
uint8_t cpu_ver; /* CPU version, usually "ff" for kvm */
-};
+} S390CPUModel;
/*
* CPU ID
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index bd0ef49fa1..6cf5fbb074 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_SUPERH_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_SUPERH_CPU "superh-cpu"
@@ -34,26 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
-/**
- * SuperHCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- * @pvr: Processor Version Register
- * @prr: Processor Revision Register
- * @cvr: Cache Version Register
- *
- * A SuperH CPU model.
- */
-struct SuperHCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-
- uint32_t pvr;
- uint32_t prr;
- uint32_t cvr;
-};
-
-
#endif
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dbe00e29c2..360eac1fbe 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -209,6 +209,26 @@ struct ArchCPU {
CPUSH4State env;
};
+/**
+ * SuperHCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
+ *
+ * A SuperH CPU model.
+ */
+struct SuperHCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+
+ uint32_t pvr;
+ uint32_t prr;
+ uint32_t cvr;
+};
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index aca29415b4..a86331bd58 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_SPARC_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#ifdef TARGET_SPARC64
#define TYPE_SPARC_CPU "sparc64-cpu"
@@ -34,21 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
-typedef struct sparc_def_t sparc_def_t;
-/**
- * SPARCCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A SPARC CPU model.
- */
-struct SPARCCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
- sparc_def_t *cpu_def;
-};
-
-
#endif
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index a808f2aff6..6999a10a40 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -249,7 +249,7 @@ typedef struct trap_state {
#endif
#define TARGET_INSN_START_EXTRA_WORDS 1
-struct sparc_def_t {
+typedef struct sparc_def_t {
const char *name;
target_ulong iu_version;
uint32_t fpu_version;
@@ -263,7 +263,7 @@ struct sparc_def_t {
uint32_t features;
uint32_t nwindows;
uint32_t maxtl;
-};
+} sparc_def_t;
#define FEATURE(X) CPU_FEATURE_BIT_##X,
enum {
@@ -567,6 +567,20 @@ struct ArchCPU {
CPUSPARCState env;
};
+/**
+ * SPARCCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A SPARC CPU model.
+ */
+struct SPARCCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+ sparc_def_t *cpu_def;
+};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_sparc_cpu;
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 2598651008..e35dc1ad2d 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -21,8 +21,6 @@
#define QEMU_TRICORE_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
-
#define TYPE_TRICORE_CPU "tricore-cpu"
@@ -31,12 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
-struct TriCoreCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
-
#endif /* QEMU_TRICORE_CPU_QOM_H */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index c537a33ee8..de3ab53a83 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -68,6 +68,12 @@ struct ArchCPU {
CPUTriCoreState env;
};
+struct TriCoreCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 03873ea50b..d932346b5f 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -30,7 +30,6 @@
#define QEMU_XTENSA_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_XTENSA_CPU "xtensa-cpu"
@@ -39,24 +38,4 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
-typedef struct XtensaConfig XtensaConfig;
-
-/**
- * XtensaCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- * @config: The CPU core configuration.
- *
- * An Xtensa CPU model.
- */
-struct XtensaCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-
- const XtensaConfig *config;
-};
-
-
#endif
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d6d2fb1f4e..dd81729306 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -426,7 +426,7 @@ extern const XtensaOpcodeTranslators xtensa_core_opcodes;
extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
extern const XtensaOpcodeTranslators xtensa_fpu_opcodes;
-struct XtensaConfig {
+typedef struct XtensaConfig {
const char *name;
uint64_t options;
XtensaGdbRegmap gdb_regmap;
@@ -489,7 +489,7 @@ struct XtensaConfig {
const xtensa_mpu_entry *mpu_bg;
bool use_first_nan;
-};
+} XtensaConfig;
typedef struct XtensaConfigList {
const XtensaConfig *config;
@@ -562,6 +562,22 @@ struct ArchCPU {
Clock *clock;
};
+/**
+ * XtensaCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @config: The CPU core configuration.
+ *
+ * An Xtensa CPU model.
+ */
+struct XtensaCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+
+ const XtensaConfig *config;
+};
#ifndef CONFIG_USER_ONLY
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 51/75] hw/cpu: Clean up global variable shadowing
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2023-11-07 12:24 ` [PULL 47/75] target: Move ArchCPUClass definition " Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 68/75] hw/sd: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
` (4 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Ani Sinha, Warner Losh, Kyle Evans,
Richard Henderson, Paolo Bonzini, Eduardo Habkost,
Marcel Apfelbaum, Yanan Wang, Laurent Vivier, David Hildenbrand,
Ilya Leoshkevich, Thomas Huth
Fix:
hw/core/machine.c:1302:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow]
const CPUArchId *cpus = possible_cpus->cpus;
^
hw/core/numa.c:69:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow]
uint16List *cpus = NULL;
^
hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the global scope [-Werror,-Wshadow]
CPUArchIdList *cpus = ms->possible_cpus;
^
hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the global scope [-Werror,-Wshadow]
unsigned cpus = config->has_cpus ? config->cpus : 0;
^
include/hw/core/cpu.h:589:17: note: previous declaration is here
extern CPUTailQ cpus;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231010115048.11856-2-philmd@linaro.org>
---
include/hw/core/cpu.h | 8 ++++----
bsd-user/main.c | 2 +-
cpu-common.c | 6 +++---
linux-user/main.c | 2 +-
target/s390x/cpu_models.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index eb943efb8f..77893d7b81 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -586,13 +586,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu)
}
typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
-extern CPUTailQ cpus;
+extern CPUTailQ cpus_queue;
-#define first_cpu QTAILQ_FIRST_RCU(&cpus)
+#define first_cpu QTAILQ_FIRST_RCU(&cpus_queue)
#define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
-#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
+#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node)
#define CPU_FOREACH_SAFE(cpu, next_cpu) \
- QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
+ QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu)
extern __thread CPUState *current_cpu;
diff --git a/bsd-user/main.c b/bsd-user/main.c
index c402fadf46..e6014f517e 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -118,7 +118,7 @@ void fork_end(int child)
*/
CPU_FOREACH_SAFE(cpu, next_cpu) {
if (cpu != thread_cpu) {
- QTAILQ_REMOVE_RCU(&cpus, cpu, node);
+ QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
}
}
mmap_fork_end(child);
diff --git a/cpu-common.c b/cpu-common.c
index 45c745ecf6..c81fd72d16 100644
--- a/cpu-common.c
+++ b/cpu-common.c
@@ -73,7 +73,7 @@ static int cpu_get_free_index(void)
return max_cpu_index;
}
-CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
+CPUTailQ cpus_queue = QTAILQ_HEAD_INITIALIZER(cpus_queue);
static unsigned int cpu_list_generation_id;
unsigned int cpu_list_generation_id_get(void)
@@ -90,7 +90,7 @@ void cpu_list_add(CPUState *cpu)
} else {
assert(!cpu_index_auto_assigned);
}
- QTAILQ_INSERT_TAIL_RCU(&cpus, cpu, node);
+ QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node);
cpu_list_generation_id++;
}
@@ -102,7 +102,7 @@ void cpu_list_remove(CPUState *cpu)
return;
}
- QTAILQ_REMOVE_RCU(&cpus, cpu, node);
+ QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu_list_generation_id++;
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 0c23584a96..0cdaf30d34 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -156,7 +156,7 @@ void fork_end(int child)
Discard information about the parent threads. */
CPU_FOREACH_SAFE(cpu, next_cpu) {
if (cpu != thread_cpu) {
- QTAILQ_REMOVE_RCU(&cpus, cpu, node);
+ QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
}
}
qemu_init_cpu_list();
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 4dead48650..5c455d00c0 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -757,7 +757,7 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
const S390CPUDef *def = s390_find_cpu_def(type, gen, ec_ga, NULL);
g_assert(def);
- g_assert(QTAILQ_EMPTY_RCU(&cpus));
+ g_assert(QTAILQ_EMPTY_RCU(&cpus_queue));
/* build the CPU model */
s390_qemu_cpu_model.def = def;
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 68/75] hw/sd: Declare QOM types using DEFINE_TYPES() macro
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2023-11-07 12:24 ` [PULL 51/75] hw/cpu: Clean up global variable shadowing Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 72/75] MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section Philippe Mathieu-Daudé
` (3 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Philippe Mathieu-Daudé, Cédric Le Goater, Peter Maydell,
Andrew Jeffery, Joel Stanley, Edgar E. Iglesias, Alistair Francis,
Bin Meng, Tyrone Ting, Hao Wu
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Mechanical transformation using the following comby script:
[pattern-x1]
match='''
static const TypeInfo :[i1~.*_info] = {
:[body]
};
static void :[rt1~.*_register_type.](void)
{
type_register_static(&:[i2~.*_info]);
}
type_init(:[rt2~.*_register_type.])
'''
rewrite='''
static const TypeInfo :[i1][] = {
{
:[body]
},
};
DEFINE_TYPES(:[i1])
'''
rule='where :[i1] == :[i2], :[rt1] == :[rt2]'
[pattern-x2]
match='''
static const TypeInfo :[i1a~.*_info] = {
:[body1]
};
...
static const TypeInfo :[i2a~.*_info] = {
:[body2]
};
static void :[rt1~.*_register_type.](void)
{
type_register_static(&:[i1b~.*_info]);
type_register_static(&:[i2b~.*_info]);
}
type_init(:[rt2~.*_register_type.])
'''
rewrite='''
static const TypeInfo :[i1a][] = {
{
:[body1]
},
{
:[body2]
},
};
DEFINE_TYPES(:[i1a])
'''
rule='''
where
:[i1a] == :[i1b],
:[i2a] == :[i2b],
:[rt1] == :[rt2]
'''
and re-indented manually.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231031080603.86889-2-philmd@linaro.org>
---
hw/sd/aspeed_sdhci.c | 19 ++++++++-----------
hw/sd/bcm2835_sdhost.c | 33 ++++++++++++++-------------------
hw/sd/cadence_sdhci.c | 21 +++++++++------------
hw/sd/core.c | 19 ++++++++-----------
hw/sd/npcm7xx_sdhci.c | 21 +++++++++------------
hw/sd/pl181.c | 35 +++++++++++++++--------------------
hw/sd/pxa2xx_mmci.c | 35 +++++++++++++++--------------------
hw/sd/sd.c | 37 ++++++++++++++++---------------------
hw/sd/sdhci-pci.c | 25 +++++++++++--------------
hw/sd/ssi-sd.c | 19 ++++++++-----------
10 files changed, 113 insertions(+), 151 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index be8cafd65f..e53206d959 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -198,16 +198,13 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
device_class_set_props(dc, aspeed_sdhci_properties);
}
-static const TypeInfo aspeed_sdhci_info = {
- .name = TYPE_ASPEED_SDHCI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(AspeedSDHCIState),
- .class_init = aspeed_sdhci_class_init,
+static const TypeInfo aspeed_sdhci_types[] = {
+ {
+ .name = TYPE_ASPEED_SDHCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSDHCIState),
+ .class_init = aspeed_sdhci_class_init,
+ },
};
-static void aspeed_sdhci_register_types(void)
-{
- type_register_static(&aspeed_sdhci_info);
-}
-
-type_init(aspeed_sdhci_register_types)
+DEFINE_TYPES(aspeed_sdhci_types)
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
index 9431c35914..a600cf39e2 100644
--- a/hw/sd/bcm2835_sdhost.c
+++ b/hw/sd/bcm2835_sdhost.c
@@ -436,24 +436,19 @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_sdhost;
}
-static const TypeInfo bcm2835_sdhost_info = {
- .name = TYPE_BCM2835_SDHOST,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(BCM2835SDHostState),
- .class_init = bcm2835_sdhost_class_init,
- .instance_init = bcm2835_sdhost_init,
+static const TypeInfo bcm2835_sdhost_types[] = {
+ {
+ .name = TYPE_BCM2835_SDHOST,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835SDHostState),
+ .class_init = bcm2835_sdhost_class_init,
+ .instance_init = bcm2835_sdhost_init,
+ },
+ {
+ .name = TYPE_BCM2835_SDHOST_BUS,
+ .parent = TYPE_SD_BUS,
+ .instance_size = sizeof(SDBus),
+ },
};
-static const TypeInfo bcm2835_sdhost_bus_info = {
- .name = TYPE_BCM2835_SDHOST_BUS,
- .parent = TYPE_SD_BUS,
- .instance_size = sizeof(SDBus),
-};
-
-static void bcm2835_sdhost_register_types(void)
-{
- type_register_static(&bcm2835_sdhost_info);
- type_register_static(&bcm2835_sdhost_bus_info);
-}
-
-type_init(bcm2835_sdhost_register_types)
+DEFINE_TYPES(bcm2835_sdhost_types)
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
index 75db34befe..ef4e0d74e3 100644
--- a/hw/sd/cadence_sdhci.c
+++ b/hw/sd/cadence_sdhci.c
@@ -175,17 +175,14 @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
dc->vmsd = &vmstate_cadence_sdhci;
}
-static const TypeInfo cadence_sdhci_info = {
- .name = TYPE_CADENCE_SDHCI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(CadenceSDHCIState),
- .instance_init = cadence_sdhci_instance_init,
- .class_init = cadence_sdhci_class_init,
+static const TypeInfo cadence_sdhci_types[] = {
+ {
+ .name = TYPE_CADENCE_SDHCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(CadenceSDHCIState),
+ .instance_init = cadence_sdhci_instance_init,
+ .class_init = cadence_sdhci_class_init,
+ },
};
-static void cadence_sdhci_register_types(void)
-{
- type_register_static(&cadence_sdhci_info);
-}
-
-type_init(cadence_sdhci_register_types)
+DEFINE_TYPES(cadence_sdhci_types)
diff --git a/hw/sd/core.c b/hw/sd/core.c
index 30ee62c510..52d5d90045 100644
--- a/hw/sd/core.c
+++ b/hw/sd/core.c
@@ -259,16 +259,13 @@ void sdbus_reparent_card(SDBus *from, SDBus *to)
sdbus_set_readonly(to, readonly);
}
-static const TypeInfo sd_bus_info = {
- .name = TYPE_SD_BUS,
- .parent = TYPE_BUS,
- .instance_size = sizeof(SDBus),
- .class_size = sizeof(SDBusClass),
+static const TypeInfo sd_bus_types[] = {
+ {
+ .name = TYPE_SD_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(SDBus),
+ .class_size = sizeof(SDBusClass),
+ },
};
-static void sd_bus_register_types(void)
-{
- type_register_static(&sd_bus_info);
-}
-
-type_init(sd_bus_register_types)
+DEFINE_TYPES(sd_bus_types)
diff --git a/hw/sd/npcm7xx_sdhci.c b/hw/sd/npcm7xx_sdhci.c
index b2f5b4a542..9958680090 100644
--- a/hw/sd/npcm7xx_sdhci.c
+++ b/hw/sd/npcm7xx_sdhci.c
@@ -166,17 +166,14 @@ static void npcm7xx_sdhci_instance_init(Object *obj)
TYPE_SYSBUS_SDHCI);
}
-static const TypeInfo npcm7xx_sdhci_info = {
- .name = TYPE_NPCM7XX_SDHCI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(NPCM7xxSDHCIState),
- .instance_init = npcm7xx_sdhci_instance_init,
- .class_init = npcm7xx_sdhci_class_init,
+static const TypeInfo npcm7xx_sdhci_types[] = {
+ {
+ .name = TYPE_NPCM7XX_SDHCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxSDHCIState),
+ .instance_init = npcm7xx_sdhci_instance_init,
+ .class_init = npcm7xx_sdhci_class_init,
+ },
};
-static void npcm7xx_sdhci_register_types(void)
-{
- type_register_static(&npcm7xx_sdhci_info);
-}
-
-type_init(npcm7xx_sdhci_register_types)
+DEFINE_TYPES(npcm7xx_sdhci_types)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 5e554bd467..2b33814d83 100644
--- a/hw/sd/pl181.c
+++ b/hw/sd/pl181.c
@@ -519,14 +519,6 @@ static void pl181_class_init(ObjectClass *klass, void *data)
k->user_creatable = false;
}
-static const TypeInfo pl181_info = {
- .name = TYPE_PL181,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(PL181State),
- .instance_init = pl181_init,
- .class_init = pl181_class_init,
-};
-
static void pl181_bus_class_init(ObjectClass *klass, void *data)
{
SDBusClass *sbc = SD_BUS_CLASS(klass);
@@ -535,17 +527,20 @@ static void pl181_bus_class_init(ObjectClass *klass, void *data)
sbc->set_readonly = pl181_set_readonly;
}
-static const TypeInfo pl181_bus_info = {
- .name = TYPE_PL181_BUS,
- .parent = TYPE_SD_BUS,
- .instance_size = sizeof(SDBus),
- .class_init = pl181_bus_class_init,
+static const TypeInfo pl181_info[] = {
+ {
+ .name = TYPE_PL181,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PL181State),
+ .instance_init = pl181_init,
+ .class_init = pl181_class_init,
+ },
+ {
+ .name = TYPE_PL181_BUS,
+ .parent = TYPE_SD_BUS,
+ .instance_size = sizeof(SDBus),
+ .class_init = pl181_bus_class_init,
+ },
};
-static void pl181_register_types(void)
-{
- type_register_static(&pl181_info);
- type_register_static(&pl181_bus_info);
-}
-
-type_init(pl181_register_types)
+DEFINE_TYPES(pl181_info)
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
index 4749e935d8..5e8ea69188 100644
--- a/hw/sd/pxa2xx_mmci.c
+++ b/hw/sd/pxa2xx_mmci.c
@@ -575,25 +575,20 @@ static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
sbc->set_readonly = pxa2xx_mmci_set_readonly;
}
-static const TypeInfo pxa2xx_mmci_info = {
- .name = TYPE_PXA2XX_MMCI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(PXA2xxMMCIState),
- .instance_init = pxa2xx_mmci_instance_init,
- .class_init = pxa2xx_mmci_class_init,
+static const TypeInfo pxa2xx_mmci_types[] = {
+ {
+ .name = TYPE_PXA2XX_MMCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PXA2xxMMCIState),
+ .instance_init = pxa2xx_mmci_instance_init,
+ .class_init = pxa2xx_mmci_class_init,
+ },
+ {
+ .name = TYPE_PXA2XX_MMCI_BUS,
+ .parent = TYPE_SD_BUS,
+ .instance_size = sizeof(SDBus),
+ .class_init = pxa2xx_mmci_bus_class_init,
+ },
};
-static const TypeInfo pxa2xx_mmci_bus_info = {
- .name = TYPE_PXA2XX_MMCI_BUS,
- .parent = TYPE_SD_BUS,
- .instance_size = sizeof(SDBus),
- .class_init = pxa2xx_mmci_bus_class_init,
-};
-
-static void pxa2xx_mmci_register_types(void)
-{
- type_register_static(&pxa2xx_mmci_info);
- type_register_static(&pxa2xx_mmci_bus_info);
-}
-
-type_init(pxa2xx_mmci_register_types)
+DEFINE_TYPES(pxa2xx_mmci_types)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 4823befdef..1106ff7d78 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -2278,16 +2278,6 @@ static void sd_class_init(ObjectClass *klass, void *data)
sc->proto = &sd_proto_sd;
}
-static const TypeInfo sd_info = {
- .name = TYPE_SD_CARD,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(SDState),
- .class_size = sizeof(SDCardClass),
- .class_init = sd_class_init,
- .instance_init = sd_instance_init,
- .instance_finalize = sd_instance_finalize,
-};
-
/*
* We do not model the chip select pin, so allow the board to select
* whether card should be in SSI or MMC/SD mode. It is also up to the
@@ -2303,16 +2293,21 @@ static void sd_spi_class_init(ObjectClass *klass, void *data)
sc->proto = &sd_proto_spi;
}
-static const TypeInfo sd_spi_info = {
- .name = TYPE_SD_CARD_SPI,
- .parent = TYPE_SD_CARD,
- .class_init = sd_spi_class_init,
+static const TypeInfo sd_types[] = {
+ {
+ .name = TYPE_SD_CARD,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(SDState),
+ .class_size = sizeof(SDCardClass),
+ .class_init = sd_class_init,
+ .instance_init = sd_instance_init,
+ .instance_finalize = sd_instance_finalize,
+ },
+ {
+ .name = TYPE_SD_CARD_SPI,
+ .parent = TYPE_SD_CARD,
+ .class_init = sd_spi_class_init,
+ },
};
-static void sd_register_types(void)
-{
- type_register_static(&sd_info);
- type_register_static(&sd_spi_info);
-}
-
-type_init(sd_register_types)
+DEFINE_TYPES(sd_types)
diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c
index c737c8b930..9b7bee8b3f 100644
--- a/hw/sd/sdhci-pci.c
+++ b/hw/sd/sdhci-pci.c
@@ -68,20 +68,17 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
sdhci_common_class_init(klass, data);
}
-static const TypeInfo sdhci_pci_info = {
- .name = TYPE_PCI_SDHCI,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(SDHCIState),
- .class_init = sdhci_pci_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
+static const TypeInfo sdhci_pci_types[] = {
+ {
+ .name = TYPE_PCI_SDHCI,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(SDHCIState),
+ .class_init = sdhci_pci_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
},
};
-static void sdhci_pci_register_type(void)
-{
- type_register_static(&sdhci_pci_info);
-}
-
-type_init(sdhci_pci_register_type)
+DEFINE_TYPES(sdhci_pci_types)
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index 167c03b780..a6cc1ad6c8 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -403,16 +403,13 @@ static void ssi_sd_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
-static const TypeInfo ssi_sd_info = {
- .name = TYPE_SSI_SD,
- .parent = TYPE_SSI_PERIPHERAL,
- .instance_size = sizeof(ssi_sd_state),
- .class_init = ssi_sd_class_init,
+static const TypeInfo ssi_sd_types[] = {
+ {
+ .name = TYPE_SSI_SD,
+ .parent = TYPE_SSI_PERIPHERAL,
+ .instance_size = sizeof(ssi_sd_state),
+ .class_init = ssi_sd_class_init,
+ },
};
-static void ssi_sd_register_types(void)
-{
- type_register_static(&ssi_sd_info);
-}
-
-type_init(ssi_sd_register_types)
+DEFINE_TYPES(ssi_sd_types)
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 72/75] MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2023-11-07 12:24 ` [PULL 68/75] hw/sd: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 73/75] MAINTAINERS: Add more guest-agent related files to the corresponding section Philippe Mathieu-Daudé
` (2 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Thomas Huth, Max Filippov, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
These machines are the only user of the mx_pic code, so the
header (which is currently "unmaintained" according to the
MAINTAINERS file) should be added to this section.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231107102104.14342-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2a17decd31..2a9354e695 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1861,6 +1861,7 @@ M: Max Filippov <jcmvbkbc@gmail.com>
S: Maintained
F: hw/xtensa/xtfpga.c
F: hw/net/opencores_eth.c
+F: include/hw/xtensa/mx_pic.h
Devices
-------
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 73/75] MAINTAINERS: Add more guest-agent related files to the corresponding section
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2023-11-07 12:24 ` [PULL 72/75] MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 75/75] dump: Add close fd on error return to avoid resource leak Philippe Mathieu-Daudé
2023-11-08 14:19 ` [PULL 00/75] Misc HW/UI patches for 2023-11-07 Stefan Hajnoczi
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Thomas Huth, Konstantin Kostiuk, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
contrib/systemd/qemu-guest-agent.service, tests/data/test-qga-config
and tests/data/test-qga-os-release belong to the guest agent, so make
sure that these files are covered here, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-ID: <20231107101811.14189-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2a9354e695..bc69253a25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3145,10 +3145,11 @@ M: Michael Roth <michael.roth@amd.com>
M: Konstantin Kostiuk <kkostiuk@redhat.com>
S: Maintained
F: qga/
+F: contrib/systemd/qemu-guest-agent.service
F: docs/interop/qemu-ga.rst
F: docs/interop/qemu-ga-ref.rst
F: scripts/qemu-guest-agent/
-F: tests/unit/test-qga.c
+F: tests/*/test-qga*
T: git https://github.com/mdroth/qemu.git qga
QEMU Guest Agent Win32
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 75/75] dump: Add close fd on error return to avoid resource leak
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2023-11-07 12:24 ` [PULL 73/75] MAINTAINERS: Add more guest-agent related files to the corresponding section Philippe Mathieu-Daudé
@ 2023-11-07 12:24 ` Philippe Mathieu-Daudé
2023-11-08 14:19 ` [PULL 00/75] Misc HW/UI patches for 2023-11-07 Stefan Hajnoczi
16 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-11-07 12:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, qemu-arm, qemu-block, qemu-s390x, qemu-riscv,
Zongmin Zhou, Zongmin Zhou, Marc-André Lureau,
Philippe Mathieu-Daudé
From: Zongmin Zhou <min_halo@163.com>
Reported-by: Coverity CID 1523842 (RESOURCE_LEAK)
Fixes: e6549197f7 ("dump: Add command interface for kdump-raw formats")
Signed-off-by: Zongmin Zhou <zhouzongmin@kylinos.cn>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231107024417.585475-1-min_halo@163.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
dump/dump.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/dump/dump.c b/dump/dump.c
index 1c304cadfd..ad5294e853 100644
--- a/dump/dump.c
+++ b/dump/dump.c
@@ -2160,6 +2160,7 @@ void qmp_dump_guest_memory(bool paging, const char *protocol,
return;
}
if (kdump_raw && lseek(fd, 0, SEEK_CUR) == (off_t) -1) {
+ close(fd);
error_setg(errp, "kdump-raw formats require a seekable file");
return;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PULL 00/75] Misc HW/UI patches for 2023-11-07
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2023-11-07 12:24 ` [PULL 75/75] dump: Add close fd on error return to avoid resource leak Philippe Mathieu-Daudé
@ 2023-11-08 14:19 ` Stefan Hajnoczi
16 siblings, 0 replies; 18+ messages in thread
From: Stefan Hajnoczi @ 2023-11-08 14:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, qemu-ppc, qemu-arm, qemu-block, qemu-s390x,
qemu-riscv, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2023-11-08 14:23 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-07 12:24 [PULL 00/75] Misc HW/UI patches for 2023-11-07 Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h' Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 37/75] target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h' Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 38/75] target/ppc: Move PowerPCCPUClass definition " Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 39/75] target/ppc: Move powerpc_excp_t " Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 40/75] target/ppc: Move powerpc_mmu_t " Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 41/75] target/ppc: Move powerpc_input_t " Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 42/75] hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 43/75] hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU* Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 44/75] target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 45/75] target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h' Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 47/75] target: Move ArchCPUClass definition " Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 51/75] hw/cpu: Clean up global variable shadowing Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 68/75] hw/sd: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 72/75] MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 73/75] MAINTAINERS: Add more guest-agent related files to the corresponding section Philippe Mathieu-Daudé
2023-11-07 12:24 ` [PULL 75/75] dump: Add close fd on error return to avoid resource leak Philippe Mathieu-Daudé
2023-11-08 14:19 ` [PULL 00/75] Misc HW/UI patches for 2023-11-07 Stefan Hajnoczi
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