From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] hw/arm/virt: fix GIC maintenance IRQ registration
Date: Fri, 10 Nov 2023 11:45:37 +0000 [thread overview]
Message-ID: <20231110114537.GA3358536@myrica> (raw)
In-Reply-To: <CAFEAcA_Jja7MT_cSiEJ2it+wG7LnUXfnuoo1vmoUf1-+KSgtAA@mail.gmail.com>
On Fri, Nov 10, 2023 at 10:19:30AM +0000, Peter Maydell wrote:
> On Fri, 10 Nov 2023 at 09:07, Jean-Philippe Brucker
> <jean-philippe@linaro.org> wrote:
> >
> > Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"),
> > GIC maintenance IRQ registration fails on arm64:
> >
> > [ 0.979743] kvm [1]: Cannot register interrupt 9
> >
> > That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case
> > where the maintenance IRQ is actually referred by its PPI index. Just
> > like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use
> > INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there
> > shouldn't be more similar issues.
> >
> > Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
> > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
>
> Isn't this already fixed by commit fa68ecb330dbd ?
No, that commit fixed the PMU interrupt (I copied most of its commit
message and referenced it), but the GIC maintenance interrupt still needed
to be fixed.
Thanks,
Jean
next prev parent reply other threads:[~2023-11-10 11:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-10 9:05 [PATCH] hw/arm/virt: fix GIC maintenance IRQ registration Jean-Philippe Brucker
2023-11-10 10:19 ` Peter Maydell
2023-11-10 11:45 ` Jean-Philippe Brucker [this message]
2023-11-13 13:14 ` Peter Maydell
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