From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH 08/11] target/hppa: Introduce MMU_IDX_MMU_DISABLED
Date: Fri, 10 Nov 2023 17:32:09 -0800 [thread overview]
Message-ID: <20231111013212.229673-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231111013212.229673-1-richard.henderson@linaro.org>
Reduce the number of direct checks against MMU_PHYS_IDX.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 1 +
target/hppa/mem_helper.c | 4 ++--
target/hppa/translate.c | 20 +++++++++++---------
3 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index cecec59700..6c0f104661 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -41,6 +41,7 @@
#define MMU_USER_P_IDX 14
#define MMU_PHYS_IDX 15
+#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) == MMU_PHYS_IDX)
#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index a13f200359..af8e86699d 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -367,8 +367,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx);
/* Failure. Raise the indicated exception. */
- raise_exception_with_ior(env, excp, retaddr,
- addr, mmu_idx == MMU_PHYS_IDX);
+ raise_exception_with_ior(env, excp, retaddr, addr,
+ MMU_IDX_MMU_DISABLED(mmu_idx));
}
trace_hppa_tlb_fill_success(env, addr & TARGET_PAGE_MASK,
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index bb1b65fef0..727dd8a829 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -69,9 +69,11 @@ typedef struct DisasContext {
} DisasContext;
#ifdef CONFIG_USER_ONLY
-#define UNALIGN(C) (C)->unalign
+#define UNALIGN(C) (C)->unalign
+#define MMU_DISABLED(C) false
#else
-#define UNALIGN(C) MO_ALIGN
+#define UNALIGN(C) MO_ALIGN
+#define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx)
#endif
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
@@ -1375,7 +1377,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
- ctx->mmu_idx == MMU_PHYS_IDX);
+ MMU_DISABLED(ctx));
tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
@@ -1393,7 +1395,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
- ctx->mmu_idx == MMU_PHYS_IDX);
+ MMU_DISABLED(ctx));
tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
@@ -1411,7 +1413,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
- ctx->mmu_idx == MMU_PHYS_IDX);
+ MMU_DISABLED(ctx));
tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
@@ -1429,7 +1431,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
- ctx->mmu_idx == MMU_PHYS_IDX);
+ MMU_DISABLED(ctx));
tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
@@ -3078,7 +3080,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
}
form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0,
- a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX);
+ a->disp, a->sp, a->m, MMU_DISABLED(ctx));
/*
* For hppa1.1, LDCW is undefined unless aligned mod 16.
@@ -3108,7 +3110,7 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a)
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m,
- ctx->mmu_idx == MMU_PHYS_IDX);
+ MMU_DISABLED(ctx));
val = load_gpr(ctx, a->r);
if (a->a) {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
@@ -3142,7 +3144,7 @@ static bool trans_stdby(DisasContext *ctx, arg_stby *a)
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m,
- ctx->mmu_idx == MMU_PHYS_IDX);
+ MMU_DISABLED(ctx));
val = load_gpr(ctx, a->r);
if (a->a) {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
--
2.34.1
next prev parent reply other threads:[~2023-11-11 1:33 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-11 1:32 [PATCH for-8.2 00/11] target/hppa: PA2.0 fixes Richard Henderson
2023-11-11 1:32 ` [PATCH 01/11] target/hppa: Update to SeaBIOS-hppa version 11 Richard Henderson
2023-11-12 17:05 ` Philippe Mathieu-Daudé
2023-11-12 18:10 ` Helge Deller
2023-11-11 1:32 ` [PATCH 02/11] hw/hppa: Require at least " Richard Henderson
2023-11-11 1:32 ` [PATCH 03/11] target/hppa: Mask reserved PSW bits in expand_sm_imm Richard Henderson
2023-11-11 1:32 ` [PATCH 04/11] target/hppa: Use only low 2 immediate bits for PROBEI Richard Henderson
2023-11-12 17:07 ` Philippe Mathieu-Daudé
2023-11-11 1:32 ` [PATCH 05/11] target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe Richard Henderson
2023-11-11 1:32 ` [PATCH 06/11] target/hppa: Fix calculation of CR_IIASQ back register Richard Henderson
2023-11-11 1:32 ` [PATCH 07/11] target/hppa: Fix possible overflow in TLB size calculation Richard Henderson
2023-11-11 1:32 ` Richard Henderson [this message]
2023-11-12 17:10 ` [PATCH 08/11] target/hppa: Introduce MMU_IDX_MMU_DISABLED Philippe Mathieu-Daudé
2023-11-11 1:32 ` [PATCH 09/11] target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX Richard Henderson
2023-11-11 1:32 ` [PATCH 10/11] target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 44 Richard Henderson
2023-11-11 1:32 ` [PATCH 11/11] hw/pci-host/astro: Fix boot for C3700 machine Richard Henderson
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