From: "Román Cárdenas" <rcardenas.rod@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Román Cárdenas" <rcardenas.rod@gmail.com>
Subject: [PATCH] [PATCH] Fix SiFive E CLINT clock frequency (#1978)
Date: Mon, 13 Nov 2023 15:51:26 +0100 [thread overview]
Message-ID: <20231113145126.99585-1-rcardenas.rod@gmail.com> (raw)
---
hw/riscv/sifive_e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 0d37adc542..87d9602383 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -225,7 +225,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
- RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
+ SIFIVE_E_LFCLK_DEFAULT_FREQ, false);
sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
/* AON */
--
2.39.3 (Apple Git-145)
reply other threads:[~2023-11-13 19:11 UTC|newest]
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