From: Joelle van Dyne <j@getutm.app>
To: qemu-devel@nongnu.org
Cc: Joelle van Dyne <j@getutm.app>,
Stefan Berger <stefanb@linux.ibm.com>,
Stefan Berger <stefanb@linux.vnet.ibm.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Ani Sinha <anisinha@redhat.com>, Thomas Huth <thuth@redhat.com>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH v5 02/14] tpm_crb: CTRL_RSP_ADDR is 64-bits wide
Date: Mon, 13 Nov 2023 18:09:12 -0800 [thread overview]
Message-ID: <20231114020927.62315-3-j@getutm.app> (raw)
In-Reply-To: <20231114020927.62315-1-j@getutm.app>
The register is actually 64-bits but in order to make this more clear
than the specification, we define two 32-bit registers:
CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This
deviates from the specs but is way more clear.
Previously, the only CRB device uses a fixed system address so this
was not an issue. However, once we support SysBus CRB device, the
address can be anywhere in 64-bit space.
Signed-off-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
---
include/hw/acpi/tpm.h | 3 ++-
hw/tpm/tpm_crb_common.c | 3 ++-
tests/qtest/tpm-crb-test.c | 2 +-
tests/qtest/tpm-util.c | 2 +-
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h
index 579c45f5ba..f60bfe2789 100644
--- a/include/hw/acpi/tpm.h
+++ b/include/hw/acpi/tpm.h
@@ -174,7 +174,8 @@ REG32(CRB_CTRL_CMD_SIZE, 0x58)
REG32(CRB_CTRL_CMD_LADDR, 0x5C)
REG32(CRB_CTRL_CMD_HADDR, 0x60)
REG32(CRB_CTRL_RSP_SIZE, 0x64)
-REG32(CRB_CTRL_RSP_ADDR, 0x68)
+REG32(CRB_CTRL_RSP_LADDR, 0x68)
+REG32(CRB_CTRL_RSP_HADDR, 0x6C)
REG32(CRB_DATA_BUFFER, 0x80)
#define TPM_CRB_ADDR_BASE 0xFED40000
diff --git a/hw/tpm/tpm_crb_common.c b/hw/tpm/tpm_crb_common.c
index fa463f295f..01b35808f6 100644
--- a/hw/tpm/tpm_crb_common.c
+++ b/hw/tpm/tpm_crb_common.c
@@ -197,7 +197,8 @@ void tpm_crb_reset(TPMCRBState *s, uint64_t baseaddr)
s->regs[R_CRB_CTRL_CMD_LADDR] = (uint32_t)baseaddr;
s->regs[R_CRB_CTRL_CMD_HADDR] = (uint32_t)(baseaddr >> 32);
s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE;
- s->regs[R_CRB_CTRL_RSP_ADDR] = (uint32_t)baseaddr;
+ s->regs[R_CRB_CTRL_RSP_LADDR] = (uint32_t)baseaddr;
+ s->regs[R_CRB_CTRL_RSP_HADDR] = (uint32_t)(baseaddr >> 32);
s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe),
CRB_CTRL_CMD_SIZE);
diff --git a/tests/qtest/tpm-crb-test.c b/tests/qtest/tpm-crb-test.c
index 396ae3f91c..9d30fe8293 100644
--- a/tests/qtest/tpm-crb-test.c
+++ b/tests/qtest/tpm-crb-test.c
@@ -28,7 +28,7 @@ static void tpm_crb_test(const void *data)
uint32_t csize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_SIZE);
uint64_t caddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR);
uint32_t rsize = readl(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_SIZE);
- uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_ADDR);
+ uint64_t raddr = readq(TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR);
uint8_t locstate = readb(TPM_CRB_ADDR_BASE + A_CRB_LOC_STATE);
uint32_t locctrl = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL);
uint32_t locsts = readl(TPM_CRB_ADDR_BASE + A_CRB_LOC_STS);
diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c
index 1c0319e6e7..dd02057fc0 100644
--- a/tests/qtest/tpm-util.c
+++ b/tests/qtest/tpm-util.c
@@ -25,7 +25,7 @@ void tpm_util_crb_transfer(QTestState *s,
unsigned char *rsp, size_t rsp_size)
{
uint64_t caddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_CMD_LADDR);
- uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_ADDR);
+ uint64_t raddr = qtest_readq(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_RSP_LADDR);
qtest_writeb(s, TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 1);
--
2.41.0
next prev parent reply other threads:[~2023-11-14 2:11 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 2:09 [PATCH v5 00/14] tpm: introduce TPM CRB SysBus device Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 01/14] tpm_crb: refactor common code Joelle van Dyne
2023-11-14 2:09 ` Joelle van Dyne [this message]
2023-11-14 2:09 ` [PATCH v5 03/14] tpm_ppi: refactor memory space initialization Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 04/14] tpm_crb: use a single read-as-mem/write-as-mmio mapping Joelle van Dyne
2023-11-14 15:46 ` Stefan Berger
2023-11-14 2:09 ` [PATCH v5 05/14] tpm_crb: move ACPI table building to device interface Joelle van Dyne
2023-11-14 16:37 ` Stefan Berger
2023-11-14 16:44 ` Stefan Berger
2023-11-14 19:29 ` Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 06/14] tpm-sysbus: add plug handler for TPM on SysBus Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 07/14] hw/arm/virt: connect TPM to platform bus Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 08/14] hw/loongarch/virt: " Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 09/14] tpm_tis_sysbus: move DSDT AML generation to device Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 10/14] tests: acpi: prepare for TPM CRB tests Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 11/14] tpm_crb_sysbus: introduce TPM CRB SysBus device Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 12/14] tests: acpi: implement TPM CRB tests for ARM virt Joelle van Dyne
2023-11-14 9:36 ` Marc-André Lureau
2023-11-14 13:04 ` Stefan Berger
2023-11-14 18:03 ` Stefan Berger
2023-11-14 21:05 ` Stefan Berger
2023-11-15 0:12 ` Stefan Berger
2023-11-24 0:56 ` Joelle van Dyne
2023-11-24 16:17 ` Stefan Berger
2023-11-24 16:21 ` Joelle van Dyne
2023-11-24 16:26 ` Stefan Berger
2023-11-25 2:39 ` Joelle van Dyne
2023-11-27 14:12 ` Stefan Berger
2023-11-14 2:09 ` [PATCH v5 13/14] tests: acpi: updated expected blobs for TPM CRB Joelle van Dyne
2023-11-14 2:09 ` [PATCH v5 14/14] tests: add TPM-CRB sysbus tests for aarch64 Joelle van Dyne
2023-11-14 9:38 ` [PATCH v5 00/14] tpm: introduce TPM CRB SysBus device Marc-André Lureau
2023-11-14 19:25 ` Joelle van Dyne
2023-11-20 8:29 ` Marc-André Lureau
2023-11-20 15:01 ` Stefan Berger
2024-04-30 11:54 ` Peter Maydell
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