From: Zhao Liu <zhao1.liu@linux.intel.com>
To: Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Babu Moger <babu.moger@amd.com>,
Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>,
Yanan Wang <wangyanan55@huawei.com>
Subject: [PATCH v6 11/16] tests: Add test case of APIC ID for module level parsing
Date: Fri, 17 Nov 2023 15:51:01 +0800 [thread overview]
Message-ID: <20231117075106.432499-12-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20231117075106.432499-1-zhao1.liu@linux.intel.com>
From: Zhuocheng Ding <zhuocheng.ding@intel.com>
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/unit/test-x86-topo.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c
index f21b8a5d95c2..55b731ccae55 100644
--- a/tests/unit/test-x86-topo.c
+++ b/tests/unit/test-x86-topo.c
@@ -37,6 +37,7 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 0);
g_assert_cmpuint(apicid_core_width(&topo_info), ==, 0);
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 0);
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
@@ -74,13 +75,22 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 33, 2};
g_assert_cmpuint(apicid_core_width(&topo_info), ==, 6);
- topo_info = (X86CPUTopoInfo) {1, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {1, 6, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 7, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 8, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 9, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 4);
+
+ topo_info = (X86CPUTopoInfo) {1, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
- topo_info = (X86CPUTopoInfo) {2, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {2, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 1);
- topo_info = (X86CPUTopoInfo) {3, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {3, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
- topo_info = (X86CPUTopoInfo) {4, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {4, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
@@ -91,6 +101,7 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 6, 3};
g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2);
g_assert_cmpuint(apicid_core_offset(&topo_info), ==, 2);
+ g_assert_cmpuint(apicid_module_offset(&topo_info), ==, 5);
g_assert_cmpuint(apicid_die_offset(&topo_info), ==, 5);
g_assert_cmpuint(apicid_pkg_offset(&topo_info), ==, 5);
--
2.34.1
next prev parent reply other threads:[~2023-11-17 7:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 7:50 [PATCH v6 00/16] Support smp.clusters for x86 in QEMU Zhao Liu
2023-11-17 7:50 ` [PATCH v6 01/16] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-11-17 7:50 ` [PATCH v6 02/16] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-11-17 7:50 ` [PATCH v6 03/16] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-11-17 7:50 ` [PATCH v6 04/16] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2023-11-17 7:50 ` [PATCH v6 05/16] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2023-11-17 7:50 ` [PATCH v6 06/16] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-11-17 7:50 ` [PATCH v6 07/16] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-11-17 7:50 ` [PATCH v6 08/16] i386: Expose module level in CPUID[0x1F] Zhao Liu
2023-11-17 7:50 ` [PATCH v6 09/16] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-11-17 7:51 ` [PATCH v6 10/16] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-11-17 7:51 ` Zhao Liu [this message]
2023-11-17 7:51 ` [PATCH v6 12/16] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-11-17 7:51 ` [PATCH v6 13/16] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-11-17 7:51 ` [PATCH v6 14/16] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-11-17 7:51 ` [PATCH v6 15/16] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-11-17 7:51 ` [PATCH v6 16/16] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-12-05 3:28 ` [PATCH v6 00/16] Support smp.clusters for x86 in QEMU Zhao Liu
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