From: Zhao Liu <zhao1.liu@linux.intel.com>
To: Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Babu Moger <babu.moger@amd.com>,
Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v6 16/16] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]
Date: Fri, 17 Nov 2023 15:51:06 +0800 [thread overview]
Message-ID: <20231117075106.432499-17-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20231117075106.432499-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x8000001D].EAX[bits 25:14].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
Changes since v3:
* Explain what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit
message. (Babu)
Changes since v1:
* Use cache->share_level as the parameter in
max_processor_ids_for_cache().
---
target/i386/cpu.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3ddedd6de120..b45d9eb74e67 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -483,20 +483,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- uint32_t num_sharing_cache;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
-
- /* L3 is shared among multiple cores */
- if (cache->level == 3) {
- num_sharing_cache = 1 << apicid_die_offset(topo_info);
- } else {
- num_sharing_cache = 1 << apicid_core_offset(topo_info);
- }
- *eax |= (num_sharing_cache - 1) << 14;
+ *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14;
assert(cache->line_size > 0);
assert(cache->partitions > 0);
--
2.34.1
next prev parent reply other threads:[~2023-11-17 7:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 7:50 [PATCH v6 00/16] Support smp.clusters for x86 in QEMU Zhao Liu
2023-11-17 7:50 ` [PATCH v6 01/16] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-11-17 7:50 ` [PATCH v6 02/16] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-11-17 7:50 ` [PATCH v6 03/16] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-11-17 7:50 ` [PATCH v6 04/16] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2023-11-17 7:50 ` [PATCH v6 05/16] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2023-11-17 7:50 ` [PATCH v6 06/16] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-11-17 7:50 ` [PATCH v6 07/16] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-11-17 7:50 ` [PATCH v6 08/16] i386: Expose module level in CPUID[0x1F] Zhao Liu
2023-11-17 7:50 ` [PATCH v6 09/16] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-11-17 7:51 ` [PATCH v6 10/16] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-11-17 7:51 ` [PATCH v6 11/16] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-11-17 7:51 ` [PATCH v6 12/16] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-11-17 7:51 ` [PATCH v6 13/16] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-11-17 7:51 ` [PATCH v6 14/16] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-11-17 7:51 ` [PATCH v6 15/16] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-11-17 7:51 ` Zhao Liu [this message]
2023-12-05 3:28 ` [PATCH v6 00/16] Support smp.clusters for x86 in QEMU Zhao Liu
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