qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [PULL 0/6] riscv-to-apply queue
@ 2023-11-22  5:37 Alistair Francis
  2023-11-22  5:37 ` [PULL 1/6] linux-user/riscv: Add Zicboz block size to hwprobe Alistair Francis
                   ` (7 more replies)
  0 siblings, 8 replies; 13+ messages in thread
From: Alistair Francis @ 2023-11-22  5:37 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit 8fa379170c2a12476021f5f50d6cf3f672e79e7b:

  Update version for v8.2.0-rc1 release (2023-11-21 13:56:12 -0500)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231122

for you to fetch changes up to 6bca4d7d1ff2b8857486c3ff31f5c6fc3e3984b4:

  target/riscv/cpu_helper.c: Fix mxr bit behavior (2023-11-22 14:03:37 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 8.2

This is a few bug fixes for the 8.2 release

* Add Zicboz block size to hwprobe
* Creat the virt machine FDT before machine init is complete
* Don't verify ISA compatibility for zicntr and zihpm
* Fix SiFive E CLINT clock frequency
* Fix invalid exception on MMU translation stage
* Fix mxr bit behavior

----------------------------------------------------------------
Clément Chigot (1):
      target/riscv: don't verify ISA compatibility for zicntr and zihpm

Daniel Henrique Barboza (1):
      hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt()

Ivan Klokov (2):
      target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
      target/riscv/cpu_helper.c: Fix mxr bit behavior

Palmer Dabbelt (1):
      linux-user/riscv: Add Zicboz block size to hwprobe

Román Cárdenas (1):
      riscv: Fix SiFive E CLINT clock frequency

 hw/riscv/sifive_e.c        |  2 +-
 hw/riscv/virt.c            | 71 +++++++++++++++++++++++++++-------------------
 linux-user/syscall.c       |  6 ++++
 target/riscv/cpu_helper.c  | 54 +++++++++++++++++------------------
 target/riscv/tcg/tcg-cpu.c |  9 ++++++
 5 files changed, 85 insertions(+), 57 deletions(-)


^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PULL 0/6] riscv-to-apply queue
@ 2020-11-10  3:56 Alistair Francis
  2020-11-10  4:00 ` Alistair Francis
  2020-11-10 10:54 ` Peter Maydell
  0 siblings, 2 replies; 13+ messages in thread
From: Alistair Francis @ 2020-11-10  3:56 UTC (permalink / raw)
  To: qemu-devel, peter.maydell; +Cc: alistair23, Alistair Francis

The following changes since commit 3c8c36c9087da957f580a9bb5ebf7814a753d1c6:

  Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201104-pull-request' into staging (2020-11-04 16:52:17 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201109

for you to fetch changes up to 96338fefc19a143abdc91f6c44f37683274b08d4:

  hw/intc/ibex_plic: Clear the claim register when read (2020-11-09 15:09:53 -0800)

----------------------------------------------------------------
This fixes two bugs in the RISC-V port. One is a bug in the
Ibex PLIC, the other fixes the Hypvervisor access functions.

----------------------------------------------------------------
Alistair Francis (6):
      target/riscv: Add a virtualised MMU Mode
      target/riscv: Set the virtualised MMU mode when doing hyp accesses
      target/riscv: Remove the HS_TWO_STAGE flag
      target/riscv: Remove the hyp load and store functions
      target/riscv: Split the Hypervisor execute load helpers
      hw/intc/ibex_plic: Clear the claim register when read

 target/riscv/cpu-param.h                |  11 ++-
 target/riscv/cpu.h                      |  19 ++++-
 target/riscv/cpu_bits.h                 |   1 -
 target/riscv/helper.h                   |   5 +-
 hw/intc/ibex_plic.c                     |   3 +
 target/riscv/cpu_helper.c               |  62 ++++++--------
 target/riscv/op_helper.c                | 124 ++-------------------------
 target/riscv/translate.c                |   2 +
 target/riscv/insn_trans/trans_rvh.c.inc | 143 ++++++++++++--------------------
 9 files changed, 115 insertions(+), 255 deletions(-)


^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-12-04  1:33 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-22  5:37 [PULL 0/6] riscv-to-apply queue Alistair Francis
2023-11-22  5:37 ` [PULL 1/6] linux-user/riscv: Add Zicboz block size to hwprobe Alistair Francis
2023-11-22  5:37 ` [PULL 2/6] hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt() Alistair Francis
2023-11-22  5:37 ` [PULL 3/6] target/riscv: don't verify ISA compatibility for zicntr and zihpm Alistair Francis
2023-11-22  5:37 ` [PULL 4/6] riscv: Fix SiFive E CLINT clock frequency Alistair Francis
2023-11-22  5:37 ` [PULL 5/6] target/riscv/cpu_helper.c: Invalid exception on MMU translation stage Alistair Francis
2023-11-22  5:38 ` [PULL 6/6] target/riscv/cpu_helper.c: Fix mxr bit behavior Alistair Francis
2023-11-22 16:50 ` [PULL 0/6] riscv-to-apply queue Stefan Hajnoczi
2023-11-25 21:08 ` Michael Tokarev
2023-12-04  1:32   ` Alistair Francis
  -- strict thread matches above, loose matches on Subject: below --
2020-11-10  3:56 Alistair Francis
2020-11-10  4:00 ` Alistair Francis
2020-11-10 10:54 ` Peter Maydell

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).