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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id f5-20020a5d64c5000000b00332ce0d7300sm41010wri.92.2023.11.22.10.30.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:30:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH-for-9.0 00/11] hw/arm: Step toward building qemu-system-{arm, aarch64} altogether Date: Wed, 22 Nov 2023 19:30:36 +0100 Message-ID: <20231122183048.17150-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This series is a step toward having a single qemu-system-aarch64 binary for both ARM and Aarch64 variants. First we add the TypeInfo::can_register() handler to QOM, to be able to decide at runtime if a type can be registered. We'll later use the target_aarch64_available() method to restrict some QOM types to the aarch64 build. Then few cleanups allow us to build the Raspi machines and its components as target-agnostic. To do that, instead of embedding a CPUState in its SoC container, we use a pointer to it. Since the type is forward-declared by "cpu-qom.h", we can use that in our hw/ headers. Then the correct CPU is instanciated by calling object_new() instead of object_initialize_child(). Finally objects are moved to meson system_ss[] source set to be built once. Does that look reasonable to keep merging TARGET_ARM/AARCH64? Thanks, Phil. Philippe Mathieu-Daudé (11): qom: Introduce the TypeInfo::can_register() handler target/arm: Add target_aarch64_available() helper target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' target/arm: Move GTIMER definitions to 'cpu-defs.h' hw/arm/bcm2836: Simplify use of 'reset-cbar' property hw/arm/bcm2836: Simplify access to 'start-powered-off' property hw/arm/bcm2836: Use ARM_CPU 'mp-affinity' property hw/arm/bcm2836: Allocate ARM CPU state with object_new() hw/arm/raspi: Build bcm2836.o and raspi.o objects once hw/intc/meson: Simplify how arm_gicv3_kvm.o objects are built include/hw/arm/bcm2836.h | 4 ++-- include/qom/object.h | 4 ++++ target/arm/cpu-defs.h | 19 ++++++++++++++++ target/arm/cpu-qom.h | 11 ++++++++++ target/arm/cpu.h | 16 +------------- hw/arm/bcm2836.c | 43 ++++++++++++++++--------------------- hw/arm/raspi.c | 8 +++---- hw/intc/arm_gicv3_its_kvm.c | 1 + hw/intc/arm_gicv3_kvm.c | 1 + qom/object.c | 3 +++ target/arm/cpu.c | 9 ++++++++ hw/arm/meson.build | 6 ++++-- hw/intc/meson.build | 6 ++++-- 13 files changed, 80 insertions(+), 51 deletions(-) create mode 100644 target/arm/cpu-defs.h -- 2.41.0