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[60.240.124.93]) by smtp.gmail.com with ESMTPSA id e4-20020a170902d38400b001cc1dff5b86sm1009070pld.244.2023.11.23.02.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 02:30:25 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , qemu-devel@nongnu.org Subject: [PATCH 0/7] ppc: pnv ChipTOD and various timebase fixes Date: Thu, 23 Nov 2023 20:30:11 +1000 Message-ID: <20231123103018.172383-1-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The chiptod/TFMR/state machine is not really tied to the other time register fixes, but they touch some of the same code, and logically same facility. Changes since v1 of chiptod patches: - Split hackish ChipTOD<->TFMR/TBST interface into its own patch - Fix multi-socket addressing on P9 / chip ID mode (P10 works) - Change chiptod primary/secondary setting to use class properties - Add more comments to explain TOD overview and timebase state machine. - SMT support for TFMR, some functionality is limited to thread 0. - FIRMWARE_CONTROL_ERROR bit implemented in TFMR. - Misc cleanups and bug fixes. The hacky part, addressing core from chiptod, is still hacky. Is there strong objection to it? This successfully runs skiboot chiptod initialisation code with POWER9 and POWER10 multi-socket, multi-core, SMT. That requires skiboot 7.1 (not in-tree), otherwise chiptod init is skipped on QEMU machines. Thanks, Nick Nicholas Piggin (7): target/ppc: Rename TBL to TB on 64-bit target/ppc: Improve timebase register defines naming target/ppc: Fix move-to timebase SPR access permissions pnv/chiptod: Add POWER9/10 chiptod model pnv/chiptod: Implement the ChipTOD to Core transfer target/ppc: Implement core timebase state machine and TFMR target/ppc: Add SMT support to time facilities include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_chiptod.h | 55 ++++ include/hw/ppc/pnv_core.h | 4 + include/hw/ppc/pnv_xscom.h | 9 + target/ppc/cpu.h | 50 +++- hw/ppc/pnv.c | 63 +++++ hw/ppc/pnv_chiptod.c | 509 +++++++++++++++++++++++++++++++++++ target/ppc/helper_regs.c | 39 ++- target/ppc/ppc-qmp-cmds.c | 4 + target/ppc/timebase_helper.c | 309 ++++++++++++++++++++- target/ppc/translate.c | 42 ++- hw/ppc/meson.build | 1 + hw/ppc/trace-events | 4 + 13 files changed, 1067 insertions(+), 25 deletions(-) create mode 100644 include/hw/ppc/pnv_chiptod.h create mode 100644 hw/ppc/pnv_chiptod.c -- 2.42.0