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[60.240.124.93]) by smtp.gmail.com with ESMTPSA id e4-20020a170902d38400b001cc1dff5b86sm1009070pld.244.2023.11.23.02.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 02:30:32 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , qemu-devel@nongnu.org Subject: [PATCH 2/7] target/ppc: Improve timebase register defines naming Date: Thu, 23 Nov 2023 20:30:13 +1000 Message-ID: <20231123103018.172383-3-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231123103018.172383-1-npiggin@gmail.com> References: <20231123103018.172383-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The timebase in ppc started out with the mftb instruction which is like mfspr but addressed timebase registers (TBRs) rather than SPRs. These instructions could be used to read TB and TBU at 268 and 269. Timebase could be written via the TBL and TBU SPRs at 284 and 285. The ISA changed around v2.03 to bring TB and TBU reads into the SPR space at 268 and 269 (access via mftb TBR-space is still supported but will be phased out). Later, VTB was added which is an entirely different register. The SPR number defines in QEMU are understandably inconsistently named. Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 8 ++++---- target/ppc/helper_regs.c | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..848e583c2d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1750,8 +1750,8 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_USPRG5 (0x105) #define SPR_USPRG6 (0x106) #define SPR_USPRG7 (0x107) -#define SPR_VTBL (0x10C) -#define SPR_VTBU (0x10D) +#define SPR_TBL (0x10C) +#define SPR_TBU (0x10D) #define SPR_SPRG0 (0x110) #define SPR_SPRG1 (0x111) #define SPR_SPRG2 (0x112) @@ -1764,8 +1764,8 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_SPRG7 (0x117) #define SPR_ASR (0x118) #define SPR_EAR (0x11A) -#define SPR_TBL (0x11C) -#define SPR_TBU (0x11D) +#define SPR_WR_TBL (0x11C) +#define SPR_WR_TBU (0x11D) #define SPR_TBU40 (0x11E) #define SPR_SVR (0x11E) #define SPR_BOOKE_PIR (0x11E) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8c00ed8c06..6f190ab13b 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -461,22 +461,22 @@ void register_generic_sprs(PowerPCCPU *cpu) /* Time base */ #if defined(TARGET_PPC64) - spr_register(env, SPR_VTBL, "TB", + spr_register(env, SPR_TBL, "TB", #else - spr_register(env, SPR_VTBL, "TBL", + spr_register(env, SPR_TBL, "TBL", #endif &spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, SPR_NOACCESS, 0x00000000); - spr_register(env, SPR_TBL, "TBL", + spr_register(env, SPR_WR_TBL, "TBL", &spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, &spr_write_tbl, 0x00000000); - spr_register(env, SPR_VTBU, "TBU", + spr_register(env, SPR_TBU, "TBU", &spr_read_tbu, SPR_NOACCESS, &spr_read_tbu, SPR_NOACCESS, 0x00000000); - spr_register(env, SPR_TBU, "TBU", + spr_register(env, SPR_WR_TBU, "TBU", &spr_read_tbu, SPR_NOACCESS, &spr_read_tbu, &spr_write_tbu, 0x00000000); -- 2.42.0