From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH for-9.0 v11 10/18] target/riscv/tcg: add user flag for profile support
Date: Fri, 24 Nov 2023 10:26:36 +0100 [thread overview]
Message-ID: <20231124-3f0e87fb0cb17d5c9d8663f6@orel> (raw)
In-Reply-To: <20231123185122.1100436-11-dbarboza@ventanamicro.com>
On Thu, Nov 23, 2023 at 03:51:14PM -0300, Daniel Henrique Barboza wrote:
> The TCG emulation implements all the extensions described in the
> RVA22U64 profile, both mandatory and optional. The mandatory extensions
> will be enabled via the profile flag. We'll leave the optional
> extensions to be enabled by hand.
>
> Given that this is the first profile we're implementing in TCG we'll
> need some ground work first:
>
> - all profiles declared in riscv_profiles[] will be exposed to users.
> TCG is the main accelerator we're considering when adding profile
> support in QEMU, so for now it's safe to assume that all profiles in
> riscv_profiles[] will be relevant to TCG;
>
> - we'll not support user profile settings for vendor CPUs. The flags
> will still be exposed but users won't be able to change them;
>
> - profile support, albeit available for all non-vendor CPUs, will be
> based on top of the new 'rv64i' CPU. Setting a profile to 'true' means
> enable all mandatory extensions of this profile, setting it to 'false'
> will disable all mandatory profile extensions of the CPU, which will
> obliterate preset defaults. This is not a problem for a bare CPU like
> rv64i but it can allow for silly scenarios when using other CPUs. E.g.
> an user can do "-cpu rv64,rva22u64=false" and have a bunch of default
> rv64 extensions disabled. The recommended way of using profiles is the
> rv64i CPU, but users are free to experiment.
>
> For now we'll handle multi-letter extensions only. MISA extensions need
> additional steps that we'll take care later. At this point we can boot a
> Linux buildroot using rva22u64 using the following options:
>
> -cpu rv64i,rva22u64=true,sv39=true,g=true,c=true,s=true
>
> Note that being an usermode/application profile we still need to
> explicitly set 's=true' to enable Supervisor mode to boot Linux.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 80 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-11-24 9:27 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-23 18:51 [PATCH for-9.0 v11 00/18] rv64i and rva22u64 CPUs, RVA22U64 profile support Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 01/18] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 02/18] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 03/18] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2023-11-24 9:23 ` Andrew Jones
2023-11-24 11:55 ` Daniel Henrique Barboza
2023-11-24 13:49 ` Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 04/18] target/riscv: add rv64i CPU Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 05/18] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 06/18] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 08/18] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 09/18] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 10/18] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-11-24 9:26 ` Andrew Jones [this message]
2023-11-23 18:51 ` [PATCH for-9.0 v11 11/18] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 12/18] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 13/18] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 14/18] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 15/18] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 16/18] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 17/18] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 18/18] target/riscv: add 'rva22u64' CPU Daniel Henrique Barboza
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