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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH for-9.0 5/7] target/riscv: add satp_mode profile support
Date: Fri, 24 Nov 2023 18:09:34 +0100	[thread overview]
Message-ID: <20231124-52cb65adbaa1a06f89582d73@orel> (raw)
In-Reply-To: <20231123191532.1101644-6-dbarboza@ventanamicro.com>

On Thu, Nov 23, 2023 at 04:15:30PM -0300, Daniel Henrique Barboza wrote:
> 'satp_mode' is a requirement for supervisor profiles like RVA22S64.
> User-mode/application profiles like RVA22U64 doesn't care.
> 
> Add 'satp_mode' to the profile description. If a profile requires it,
> set it during cpu_set_profile(). We'll also check it during finalize()
> to validate if the running config implements the profile.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/cpu.c         |  1 +
>  target/riscv/cpu.h         |  1 +
>  target/riscv/tcg/tcg-cpu.c | 41 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 43 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2b79fe861b..a77118549b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1543,6 +1543,7 @@ static RISCVCPUProfile RVA22U64 = {
>      .name = "rva22u64",
>      .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
>      .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> +    .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
>      .ext_offsets = {
>          CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
>          CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 485d2da3c2..6c5fceb5f5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -82,6 +82,7 @@ typedef struct riscv_cpu_profile {
>      bool enabled;
>      bool user_set;
>      int priv_spec;
> +    int satp_mode;
>      const int32_t ext_offsets[];
>  } RISCVCPUProfile;
>  
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a26cc6f093..8cfab26915 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -775,6 +775,31 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>      riscv_cpu_disable_priv_spec_isa_exts(cpu);
>  }
>  
> +#ifndef CONFIG_USER_ONLY
> +static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
> +                                            RISCVCPUProfile *profile,
> +                                            bool send_warn)
> +{
> +    int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
> +
> +    if (profile->satp_mode > satp_max) {
> +        if (send_warn) {
> +            bool is_32bit = riscv_cpu_is_32bit(cpu);
> +            const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit);
> +            const char *cur_satp = satp_mode_str(satp_max, is_32bit);
> +
> +            warn_report("Profile %s requires satp mode %s, "
> +                        "but satp mode %s was set", profile->name,
> +                        req_satp, cur_satp);
> +        }
> +
> +        return false;
> +    }
> +
> +    return true;
> +}
> +#endif
> +
>  static void riscv_cpu_validate_profile(RISCVCPU *cpu,
>                                         RISCVCPUProfile *profile)
>  {
> @@ -784,6 +809,13 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
>      bool profile_impl = true;
>      int i;
>  
> +#ifndef CONFIG_USER_ONLY
> +    if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
> +        profile_impl = riscv_cpu_validate_profile_satp(cpu, profile,
> +                                                       send_warn);
> +    }
> +#endif
> +
>      if (profile->priv_spec != env->priv_ver) {
>          profile_impl = false;
>  
> @@ -1083,10 +1115,19 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
>      profile->user_set = true;
>      profile->enabled = value;
>  
> +

stray blank line

>      if (profile->enabled) {
>          cpu->env.priv_ver = profile->priv_spec;
>      }
>  
> +#ifndef CONFIG_USER_ONLY
> +    if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
> +        const char *satp_prop = satp_mode_str(profile->satp_mode,
> +                                              riscv_cpu_is_32bit(cpu));
> +        object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
> +    }
> +#endif
> +
>      for (i = 0; misa_bits[i] != 0; i++) {
>          uint32_t bit = misa_bits[i];
>  
> -- 
> 2.41.0
>

Otherwise

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


  reply	other threads:[~2023-11-24 17:10 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-23 19:15 [PATCH for-9.0 0/7] target/riscv: implement RVA22S64 profile Daniel Henrique Barboza
2023-11-23 19:15 ` [PATCH for-9.0 1/7] target/riscv: implement svade Daniel Henrique Barboza
2023-11-24  9:52   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 2/7] target/riscv: add priv ver restriction to profiles Daniel Henrique Barboza
2023-11-24  9:57   ` Andrew Jones
2023-11-24 11:42     ` Daniel Henrique Barboza
2023-11-23 19:15 ` [PATCH for-9.0 3/7] target/riscv/cpu.c: finalize satp_mode earlier Daniel Henrique Barboza
2023-11-24 17:06   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 4/7] target/riscv/cpu: add riscv_cpu_is_32bit() Daniel Henrique Barboza
2023-11-24 17:17   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 5/7] target/riscv: add satp_mode profile support Daniel Henrique Barboza
2023-11-24 17:09   ` Andrew Jones [this message]
2023-11-23 19:15 ` [PATCH for-9.0 6/7] target/riscv: add RVA22S64 profile Daniel Henrique Barboza
2023-11-24 17:16   ` Andrew Jones
2023-11-24 20:13     ` Daniel Henrique Barboza
2023-11-23 19:15 ` [PATCH for-9.0 7/7] target/riscv: add rva22s64 cpu Daniel Henrique Barboza
2023-11-24 17:16   ` Andrew Jones

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